3D Non-Volatile NOR Flash Memory Vertical Stacking

The patent transitions from conventional planar (2D) flash memory architecture to a three-dimensional stacked architecture. Multiple layers of memory cells are vertically stacked above the substrate, with each layer containing NOR memory cells that can be independently accessed. This vertical stacking enables significantly higher storage density while preserving the parallel connection topology that provides full random access capability.

The three-dimensional architecture divides the memory structure into multiple discrete layers, with each layer containing segmented NOR memory cells. Each layer can be independently controlled and accessed through dedicated word lines and bit lines, allowing individual cell access while maintaining high density through the stacked configuration.

Instead of connecting cells in series within a single plane, the patent stacks multiple parallel NOR memory cell arrays vertically in the third dimension. Each layer maintains parallel cell connections, and selective access to individual layers through vertical word lines enables random access to any cell in the stacked structure without requiring series connections.

The patent introduces intermediate control structures including layer-select transistors and vertical word lines that act as mediators between the control logic and the stacked memory cells. These intermediaries enable selective activation of specific layers and individual cells within layers, providing full random access capability while maintaining the parallel architecture needed for NOR functionality.