Multi-Die Memory Array Shared Line Architecture
Solution Overview
Problem
Conventional memory arrays face challenges in efficiently conducting digital signals across multiple dice, leading to increased resistance, capacitance, and latency, which affects transistor density, power consumption, and overall performance.
Innovation Solution
Implementing a shared line architecture where memory cells on multiple dice are coupled to a shared line, allowing for shorter signal paths and reduced resistance and capacitance, enabling more efficient digital signal transmission and increased transistor density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are distributed across multiple dice, then memory capacity is increased, but signal transmission resistance and capacitance increase
Solution Approach 1:
Multiple dice are merged into a single memory array structure where memory cells on different dice share common bit lines and word lines. The dice are interconnected through shared signal lines, allowing them to function as a unified memory system rather than separate units, thereby reducing the harmful effects of distributed architecture.
Solution Approach 2:
Shared bit lines and word lines act as intermediaries that connect memory cells across multiple dice. These shared lines serve as mediators for signal transmission, reducing the need for direct point-to-point connections between dice and thereby lowering overall resistance and capacitance in the signal path.
2Reliability
If separate lines are used for each die, then signal transmission is reliable, but device complexity and power consumption increase
Solution Approach 1:
The shared bit lines and word lines serve multiple functions: they act as data lines for reading and writing operations, as selection lines for addressing memory cells, and as interconnects between multiple dice. This multi-functionality reduces the total number of lines required compared to dedicated separate lines for each die.
Solution Approach 2:
Multiple dedicated lines for individual dice are merged into shared lines that serve all dice simultaneously. This consolidation reduces device complexity by eliminating redundant line structures while maintaining reliable signal transmission through the shared architecture.
3Quantity of substance
If longer signal paths are used to connect memory cells across dice, then memory capacity is increased, but latency increases
Solution Approach 1:
The memory array is organized in a multi-dimensional structure where memory cells are arranged in rows and columns that span across multiple dice. This dimensional organization allows for shorter physical signal paths within each die while maintaining large total capacity through the multi-die arrangement, effectively reducing latency by exploiting the spatial dimensionality of the memory structure.
Data Source
AI summary
For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.