Single-Poly SOI Memory Cell with Fowler-Nordheim Tunneling
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Solution Overview
Problem
Existing non-volatile memory (NVM) cells using single polysilicon layers face challenges in achieving efficient erasure without high current consumption and require significant space due to the need for multiple transistors and capacitors, while those with control gates suffer from high current usage or inability to erase individual cells electrically.
Innovation Solution
A non-volatile memory cell design utilizing a single polysilicon layer with interconnected capacitors and transistors, employing Fowler-Nordheim tunneling for both programming and erasing, and sharing capacitors between cells to reduce space and current consumption, with selection mechanisms to control cell operations during read, program, and erase modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If hot electrons and impact ionization are used to program memory cells, then programming capability is achieved, but current consumption increases significantly
Solution Approach 1:
The patent replaces the hot electron injection mechanism (which requires high current) with Fowler-Nordheim tunneling through a thin oxide layer. This substitution of the physical mechanism enables programming with much lower current consumption while maintaining the ability to inject electrons into the floating gate for memory programming.
Solution Approach 2:
The patent changes the key parameter of the tunnel oxide thickness to approximately 5nm or less, which enables Fowler-Nordheim tunneling to occur at practical voltage levels. This parameter change allows electron injection without requiring the high currents associated with hot electron mechanisms, thus reducing power consumption while maintaining programming capability.
2Device complexity
If a single polysilicon layer is used, then device complexity is reduced, but the ability to achieve efficient electrical erasure is compromised
Solution Approach 1:
The single polysilicon layer is designed to serve multiple functions: it acts as the control gate for the transistor, the floating gate for charge storage, and the electrode for Fowler-Nordheim tunneling during both programming and erasing operations. This multi-functionality enables electrical erasure capability while maintaining the simplicity of a single polysilicon layer structure.
Solution Approach 2:
The patent introduces a thin oxide layer as an intermediary between the single polysilicon layer and the underlying semiconductor substrate. This oxide layer enables Fowler-Nordheim tunneling during erasing operations, allowing electrical erasure of individual cells without requiring additional polysilicon layers or complex structures.
3Ease of operation
If multiple transistors and capacitors are used to achieve electrical erasure, then erasure capability is improved, but device area increases significantly
Solution Approach 1:
The patent merges the control gate and floating gate functions into a single polysilicon layer structure. The same polysilicon region that forms the transistor gate also serves as the floating gate for charge storage and the tunneling electrode for erasing. This merging eliminates the need for separate transistors and capacitors that would be required in conventional architectures, significantly reducing the memory cell area while maintaining electrical erasure capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances memory cell density by using a single polysilicon layer, reduces current consumption, and allows for electrical erasure of individual cells without the need for multiple transistors or extensive space, while maintaining efficient operation under high voltages.
Implementation Method 1
both programming and erasing by Fowler-Nordheim tunneling, which is achieved by providing a potential difference across the drain 204 and control gate 208 of the order of 20V
Data Source
AI summary
In a non-volatile memory cell, a single poly SOI technology is used to save space and achieve low current programming by providing two capacitors formed in an n-material over an NBL, forming a inverter in an n-material over a PBL, and isolating the NBL from the PBL by means of a lightly doped region or a deep trench isolation region.