Semiconductor Pillar Gate Structure for High Integration Density
Solution Overview
Problem
The increasing integration density of semiconductor devices, particularly in MOS transistors, leads to challenges in suppressing leakage current and reducing circuit area, making it difficult to achieve high integration while maintaining effective gate length and production efficiency.
Innovation Solution
A semiconductor device configuration featuring multiple gate insulating films and gates surrounding pillar-shaped semiconductor layers, with connected gates and insulating films, allows for reduced gate recess heights, enabling shorter atomic layer deposition times and more efficient metal deposition, thus enhancing integration density and production efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple silicon pillars are formed on a surface to achieve high integration, then the integration degree increases, but the area occupied increases and leakage current suppression becomes difficult
Solution Approach 1:
The patent merges nMOS and pMOS transistors into a single shared silicon pillar structure. Multiple gate electrodes surround the same pillar, with n-type and p-type semiconductor layers formed within the same pillar volume. This allows two transistors to occupy the area of one pillar, effectively doubling integration density without increasing the footprint area.
Solution Approach 2:
The patent transitions from planar transistor layouts to a three-dimensional surrounding gate structure. Gate electrodes are positioned around the pillar in multiple directions, creating vertical and radial control of the channel. This dimensional change allows multiple gates to control a single pillar, achieving higher integration in the vertical dimension rather than expanding horizontally.
2Productivity
If gate recess height is reduced to shorten atomic layer deposition time, then production efficiency increases, but gate length control becomes more difficult
Solution Approach 1:
The patent performs preliminary formation of the pillar-shaped semiconductor layer with precise dimensional control before gate deposition. The pillar is formed with a predetermined height and diameter that accommodates the gate structure. By pre-establishing the pillar geometry, the subsequent gate deposition process becomes simpler and faster, as the recess depth is already determined by the pillar dimensions rather than requiring deep etching.
Solution Approach 2:
The patent changes the parameter of gate recess height to a smaller value, which directly reduces the atomic layer deposition time for metal gates. The surrounding gate configuration allows the gate to be formed at a shallower recess depth while still achieving sufficient gate length control through the multi-directional gate electrode arrangement around the pillar.
3Manufacturing precision
If extensive metal deposition is performed to achieve doubled gate length, then gate control improves, but production time increases
Solution Approach 1:
The patent achieves extended gate length control by arranging gate electrodes in multiple dimensions around the pillar rather than extending a single gate linearly. Gate electrodes are positioned radially and vertically around the pillar, providing multi-directional control of the channel. This dimensional approach achieves equivalent or superior gate control to a doubled gate length without requiring proportionally longer deposition times, as the gates are formed concurrently in a compact three-dimensional arrangement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a semiconductor device with increased integration density and reduced production time, achieving a doubled gate length without the need for extensive metal deposition, while maintaining effective insulation and transistor performance.
Implementation Method 1
depositing a first insulating film that is an oxide film containing an impurity of a first conductivity type on a fourth first-conductivity-type semiconductor layer formed on a substrate
Implementation Method 2
depositing a sixth insulating film that is a nitride film; depositing a seventh insulating film that is a nitride film
Data Source
AI summary
A method for producing a semiconductor device includes depositing a first oxide insulating film containing an impurity of a first conductivity type on a fourth first-conductivity-type semiconductor layer formed on a substrate; depositing a sixth insulating nitride film; depositing a second oxide insulating film containing an impurity of the first conductivity type; depositing a seventh insulating nitride film; depositing a third oxide insulating film containing an impurity of the first conductivity type; etching the first insulating film, the sixth insulating film, the second insulating film, and the seventh insulating film to form a contact hole; forming a first pillar-shaped silicon layer in the contact hole by epitaxial growth; removing the sixth insulating film and the seventh insulating film; forming a first gate and a second gate; and forming a contact connecting the first gate and the second gate.