Photodiode Array Fabrication via Conductive Vias and Epitaxial Doping
Solution Overview
Problem
The existing photodiode fabrication processes for imaging systems, particularly those involving detectors with integrated diode/readout electronics, are complex and costly due to the need for coordinated double-side photolithography and high-temperature processes, which are not compatible with standard CMOS fabrication capabilities.
Innovation Solution
A photodiode array is fabricated using a silicon wafer with conductive vias and a doped epitaxial layer to form diode junctions without metal processes, allowing for separate processing of the photodiode and readout electronics on different sides of the wafer, enabling high-temperature steps and compatibility with CMOS fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If ion implant process and metal process are used to form diode junction and electric connections, then photodiode fabrication is achieved, but the wafer cannot undergo high temperature processes and coordinated double-side photolithography is required
Solution Approach 1:
The patent extracts the metal process from the photodiode fabrication sequence, replacing it with a semiconductor-based contact formation process. This removal eliminates the constraint that prevents high temperature processes and simplifies the overall fabrication flow, allowing standard CMOS processes to be used without special coordination requirements.
Solution Approach 2:
The patent changes the fundamental parameter of contact formation from metal-based to semiconductor-based (using doped silicon regions). This parameter change transforms the process compatibility, enabling the wafer to withstand high temperature processes and eliminating the need for restricted process sequencing.
2Adaptability or versatility
If metal processes are used at both sides of the wafer, then electric connections are formed, but standard CMOS fabrication capabilities are exceeded and cost increases
Solution Approach 1:
The patent makes the photodiode fabrication process universal with standard CMOS processes by using semiconductor-based contact formation instead of metal processes. This allows the same fabrication facility to produce both photodiodes and readout electronics using identical process steps, eliminating the need for specialized process lines and reducing overall manufacturing cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, eliminates the need for coordinated double-sided photolithography, and allows for the integration of photodiodes and readout electronics without metal, making the process more cost-effective and compatible with CMOS technology.
Implementation Method 1
a doped epitaxial layer on the first surface, wherein the doped epitaxial layer and the substrate form a plurality of diode junctions
Implementation Method 2
a plurality of conductive vias through the silicon wafer... The plurality of photodiodes and the readout electronics are electrically connected by the plurality of conductive vias
Data Source
AI summary
Photodiode arrays and methods of fabrication are provided. One photodiode array includes a silicon wafer having a first surface and an opposite second surface and a plurality of conductive vias through the silicon wafer. The photodiode array further includes a patterned doped epitaxial layer on the first surface, wherein the patterned doped epitaxial layer and the substrate form a plurality of diode junctions. A patterned etching defines an array of the diode junctions.