SeOI Back Control Gate Transistor for Lithography Resolution Limits
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Solution Overview
Problem
The challenge in semiconductor device fabrication is the difficulty in producing transistors with varying channel widths due to the resolution limits of lithography, leading to irregularities in performance and fabrication complexity, especially in miniaturized patterns, which limits the flexibility in designing electronic circuits and increases fabrication costs.
Innovation Solution
The introduction of a semiconductor device structure on a SeOI substrate with a back control gate region formed in the base substrate beneath the channel region, allowing for the adjustment of the threshold voltage and effective channel width, enabling transistors to remain off or on regardless of the front control gate voltage, thus modulating performance characteristics without altering physical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors with different channel widths are designed to achieve desired current intensity and performance, then circuit performance is improved, but fabrication precision deteriorates due to lithography resolution limits
Solution Approach 1:
The patent changes the electrical parameter (threshold voltage) rather than the geometric parameter (channel width) to achieve performance differentiation. By applying different voltages to the back control gate, transistors with identical physical dimensions can exhibit different electrical characteristics, effectively decoupling performance tuning from geometric fabrication precision.
2Manufacturing precision
If long strips of transistors with identical dimensions are used to simplify lithography, then manufacturing precision is improved, but adaptability deteriorates since flexibility in designing circuits with varying transistor widths is lost
Solution Approach 1:
The patent enables circuit design flexibility by allowing electrical parameter modulation through back control gate voltage. Designers can achieve effective width variation by adjusting voltages rather than changing physical dimensions, thus maintaining both lithographic simplicity and design adaptability.
Solution Approach 2:
The patent introduces dynamic control of transistor characteristics through the back control gate voltage. This allows the transistor properties to be adjusted in real-time or during operation, providing adaptability without requiring different physical structures for each application.
3Area of stationary object
If miniaturized transistor patterns are fabricated to reduce device size, then area is reduced, but manufacturing precision deteriorates due to increased difficulty in controlling irregular patterns
Solution Approach 1:
The patent enables precise electrical characterization and control of miniaturized transistors by providing an additional control dimension through the back gate. This allows compensation for variability introduced by miniaturization and irregular patterns, maintaining precision despite reduced dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies lithography, reduces wafer space, and enhances the regularity and density of semiconductor device structures, achieving improved performance, reduced size, and more reliable fabrication by allowing dynamic modification of transistor conductance and leakage currents, thereby optimizing transistor performance and reducing power consumption.
Implementation Method 1
a back control gate region formed in the base substrate beneath the channel region, allowing for the adjustment of the threshold voltage and effective channel width
Data Source
AI summary
This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures.