Non-Volatile Memory Read Voltage Selection for Inner and Outer Pillars
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Solution Overview
Problem
Conventional non-volatile memory devices, such as vertical NAND flash memory, often treat data read operations from inner and outer pillar memory cell strings uniformly, despite differences in performance characteristics, leading to inefficiencies and increased read operation latency due to process variations and shifting memory cell threshold voltage distributions.
Innovation Solution
The implementation of a memory device with a read voltage determination unit that selects distinct optimal read voltages for outer and inner memory cell strings, utilizing a page buffer circuit to connect bit lines differently for each type of string, allowing for dynamic adjustment of read voltages based on candidate read voltages stored in registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If uniform read voltage is applied to all memory cell strings, then device complexity is reduced, but read operation accuracy deteriorates due to performance differences between inner and outer pillar strings
Solution Approach 1:
The memory cell array is segmented into inner pillar memory cell strings and outer pillar memory cell strings, with separate read voltage determination units for each segment. This allows independent optimization of read voltages for each group, improving read operation accuracy while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
Different read voltages are applied to different spatial locations (inner vs. outer pillars) based on their specific performance characteristics. The read voltage determination unit selects optimal read voltages tailored to each pillar group's threshold voltage distribution, implementing local quality optimization rather than uniform treatment.
2Measurement precision
If distinct optimal read voltages are selected for inner and outer memory cell strings, then read operation accuracy is improved, but device complexity increases due to additional voltage determination circuits
Solution Approach 1:
Multiple candidate read voltages are stored in a single register structure that can provide different voltages to inner and outer pillar strings. The voltage determination units share common circuitry and candidate voltage storage, merging functions to reduce overall device complexity while still providing distinct optimal voltages to each pillar group.
Solution Approach 2:
The read voltage determination units dynamically select from multiple candidate read voltages stored in registers, adapting the applied voltage based on detected threshold voltage distributions. This dynamic selection allows the system to optimize read accuracy for different operating conditions without requiring separate fixed voltage circuits for each case.
3Device complexity
If conventional uniform read operations are used, then device complexity is maintained at low level, but read operation latency increases due to process variations and threshold voltage shifts
Solution Approach 1:
Multiple candidate read voltages are pre-stored in registers before the actual read operation. The voltage determination units can quickly select from these pre-prepared voltages based on threshold voltage distribution detection, avoiding time-consuming voltage generation and adjustment during the read operation, thus reducing latency.
Solution Approach 2:
The read voltage determination units detect the threshold voltage distribution of memory cells and use this feedback information to select appropriate read voltages from candidate registers. This feedback mechanism enables adaptive voltage selection that compensates for process variations and threshold voltage shifts, improving read speed and accuracy without significantly increasing device complexity.
Data Source
AI summary
A non-volatile memory includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array region in the memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines in the memory cell region, an outer memory cell string in the memory cell region including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O) circuit in the peripheral circuit region including a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.