3D Memory Cell Structure for Higher Density With Shared Gates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Two-dimensional memory arrays are approaching scaling limits, limiting further increases in storage density.
Innovation Solution
A memory block with a three-dimensional array structure, comprising multiple memory subarray layers stacked along the height direction, where each layer includes drain, channel, and source region semiconductor strips, with gate strips arranged along the column direction, forming memory cells that share gate structures across layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory arrays are used, then manufacturing process is simple, but storage density cannot be further increased due to scaling limits
Solution Approach 1:
The patent transitions from a two-dimensional memory array to a three-dimensional stacked structure. Multiple memory subarray layers are stacked along the height direction, with each layer containing semiconductor strips arranged in row and column directions. This vertical stacking enables increased storage density by utilizing the third dimension (height) rather than only expanding in the planar directions, thereby overcoming the scaling limits of 2D arrays.
2Quantity of substance
If three-dimensional stacked structure is implemented, then storage density increases, but manufacturing complexity increases
Solution Approach 1:
The memory device is divided into multiple memory subarray layers stacked along the height direction. Each subarray layer is further segmented into semiconductor strips arranged in rows and columns. This segmentation allows for modular manufacturing where each layer can be processed and then stacked, reducing the overall manufacturing complexity compared to creating a single monolithic 3D structure.
Solution Approach 2:
Multiple memory subarray layers are combined through stacking to form a unified 3D memory structure. The gate strips from different layers are merged vertically to form shared gate structures that control multiple channel regions simultaneously. This merging reduces the total number of independent gate structures needed, thereby reducing manufacturing complexity while maintaining high storage density.
3Reliability
If multiple gate strips are arranged on each side of semiconductor strips, then memory cell functionality is achieved, but device complexity increases
Solution Approach 1:
The gate strips are designed to serve multiple functions: they control the channel region in their own layer and also control channel regions in adjacent layers through vertical stacking. This multi-functionality reduces the total number of gate structures needed compared to having separate gates for each layer, thereby reducing device complexity while maintaining reliable memory cell functionality.
Solution Approach 2:
The gate strips are arranged in a nested configuration where gate strips from different layers are vertically aligned and overlap in the height direction. This nesting allows a single gate strip structure to control multiple channel regions at different vertical levels, reducing the overall gate structure complexity while ensuring proper memory cell operation.
Data Source
AI summary
The present application provides a memory block, a memory device, and a memory cell. The memory block includes a memory array, including a plurality of memory cells distributed in a a three-dimensional array. The memory array includes a plurality of memory subarray layers, and each memory subarray layer includes a drain region semiconductor layer including a plurality of drain region semiconductor strips, a channel semiconductor layer including a plurality of channel semiconductor strips, and a source region semiconductor layer including a plurality of source region semiconductor strips. A plurality of gate strips are arranged on each side of the drain region semiconductor strip, channel semiconductor strip, and source region semiconductor strip. A part of the gate strip, a corresponding part of the channel semiconductor strip, a part of the drain region semiconductor strip, and a part of the source region semiconductor strip are configured to form a memory cell.