Static Storage TRIZ Cases
- PCRAM Cross-Point Architecture with Shared Word Lines
Shared word lines and wider metal tracks reduce PCRAM driver count and word line resistance while improving write current.
- Memory Controller Parity Mapping for Error Correction
A memory controller maps parity bits across different bit positions to improve error detection and bit-flip correction in memory devices.
- Concatenated ECC Verification for Non-Volatile Memory Reads
Concatenated error-correcting codes use staged decoding and parity evaluation to detect residual errors in non-volatile memory reads.
- Dynamic Memory Block Repairs With Universal Spares
Separate static and dynamic spare pools reduce memory capacity; universal dynamic spares support both block types with fewer reserved blocks.
- Semiconductor Memory Structure With Resistance Patterns for Spike Control
A resistance pattern between stacked column lines limits spike currents, helping protect memory cells while supporting higher integration.
- Memory-Constrained Transaction Redundancy With Address Fault Detection
Transaction redundancy circuitry uses separate memory regions and transformed addresses to detect address faults and protect data integrity.
- Multi-Stream Storage Device Parity Buffering With LRU Swapping
LRU swapping between parity-data memories helps storage devices process multi-stream data with lower latency and better resource use.
- Vertical Memory Channel Structures with Recessed Insulators
Recesses in interlayer insulating layers guide vertical memory channels to limit deep penetration and improve process yield.
- Semiconductor Failure Analysis With Fail I/O–Port Matching
Fail I/O values are matched with memory-port IDs to link logic tests and memory diagnosis, reducing manual analysis time.
- Memory Read-Path Parity Regeneration for Reliable Data Updates
During a read, parity regeneration and a write path correct cell errors and update stored data, improving memory reliability without a separate ECC engine.
- Computational Memory Test Flow Optimization for Lower Yield Loss
A computational method compares candidate memory test conditions with benchmark defects to reduce overkill, yield loss, and DPPM.
- Memory Controller Asymmetric Parity Mapping for Error Correction
Different parity bit positions across memory devices help the memory controller detect and correct errors, improving data integrity.
- Boron-Covered Semiconductor Pillars for VGAA Memory Density
See how boron-containing covering layers and gate-all-around pillars increase contact area and reduce resistance for denser dynamic memory arrays.
- Structurally Independent Non-Volatile Memory Component for SoC Scaling
Separating non-volatile memory from SoC fabrication enables larger capacity while supporting yield and reliability through dedicated flash processing.
- Memory Repair Control Using Serial Interfaces to Reduce Routing Congestion
BIST identifies fault cells while a repair-information control block sends data serially to redundancy cells, easing routing congestion and errors.
- Non-Volatile Memory Overdrive Voltage Control After Failures
When memory operations fail, the system tests adjusted word-line overdrive voltage and applies it to improve future reliability.