Concatenated ECC Verification for Non-Volatile Memory Reads
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Solution Overview
Problem
Existing memory systems face challenges in accurately determining whether error correction has been correctly performed, leading to potential erroneous corrections and data integrity issues.
Innovation Solution
A memory system employing a concatenated code of a first and second error-correcting code, where a first decoding processing is followed by generating a parity bit and calculating an evaluation value to determine the presence of errors, using a memory controller to ensure accurate decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored with error correction encoding in non-volatile memory, then data protection is improved, but the complexity of decoding and determining error correction accuracy increases
Solution Approach 1:
The error correction code is divided into two independent parts: a first error-correcting code and a second error-correcting code. The first code handles primary error correction while the second code provides additional protection and verification. This segmentation allows the decoding process to handle errors in stages, improving reliability without overwhelming complexity in a single decoding mechanism.
Solution Approach 2:
The system performs decoding using the first error-correcting code, then uses the second error-correcting code to verify the accuracy of the first decoding result. This feedback mechanism allows the system to detect and correct errors in the decoding process itself, ensuring accurate error correction while maintaining manageable complexity through structured verification.
2Reliability
If concatenated error-correcting codes are used to improve error correction accuracy, then data integrity is improved, but the decoding processing time increases
Solution Approach 1:
The decoding process is segmented into two sequential stages: first decoding with the first error-correcting code, then verification with the second error-correcting code. This segmentation allows the system to perform error correction efficiently in the first stage and then quickly verify accuracy in the second stage, improving overall error correction accuracy while keeping processing time manageable through structured approach.
Solution Approach 2:
The system performs preliminary decoding using the first error-correcting code before verification with the second code. This preliminary action completes the majority of error correction work in the first stage, and the second stage only needs to verify the results, significantly reducing the time required compared to applying both codes sequentially without the preliminary action optimization.
3Productivity
If error correction decoding is performed without verification, then decoding speed is improved, but erroneous corrections may occur
Solution Approach 1:
The second error-correcting code serves as a verification mechanism that provides feedback on the accuracy of the first decoding result. This feedback allows the system to detect erroneous corrections and correct them, ensuring high decoding accuracy while maintaining fast decoding speeds by using the first code for primary correction and the second code only for verification.
Solution Approach 2:
The system uses the second error-correcting code to self-verify the decoding results produced by the first code. This self-service verification mechanism ensures that the decoding process is both fast and accurate, as the system checks its own work without requiring external intervention or complex additional processing.
Data Source
AI summary
A memory system according to the present disclosure includes a non-volatile memory that stores a concatenated code of a first error-correcting code and a second error-correcting code, and a memory controller. When a first decoding processing using the first error-correcting code for read information read from the non-volatile memory or a checking processing of checking that the read information does not include an error succeeds, the memory controller generates a first parity bit that is a parity bit of the second error-correcting code, and calculates a first evaluation value for determining whether the read information includes the error by using the generated first parity bit and a second parity bit that is a parity bit of the second error-correcting code after second decoding processing is executed. The memory controller determines whether the read information includes the error by using the first evaluation value.