Memory Repair Control Using Serial Interfaces to Reduce Routing Congestion
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Solution Overview
Problem
Existing memory repair methods face challenges with high routing congestion and error rates due to parallel transmission of repair information, which limits the scalability and efficiency of memory repair processes in integrated circuits.
Innovation Solution
A memory repair device utilizing a serial interface method for transmitting repair information, reducing the number of routings and congestion by using a repair information control block, interface conversion circuits, and BIST circuits to detect and replace fault cells with redundancy cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel transmission method is used for repair information, then transmission speed is improved, but routing congestion and error rates increase
Solution Approach 1:
A serial interface circuit is introduced as an intermediary component between the repair information storage block and memory blocks. This serial interface converts parallel repair information into serial transmission, acting as a mediator that reduces routing congestion while maintaining reliable data transfer. The serial interface includes transmission control logic that manages the conversion and transmission process, effectively resolving the contradiction between transmission speed and error rate.
2Speed
If parallel transmission method is used for repair information, then transmission speed is improved, but routing congestion increases
Solution Approach 1:
The patent transitions from parallel transmission (multiple simultaneous data paths) to serial transmission (single sequential data path), effectively changing the dimension of data transmission. This dimensional change from parallel to serial reduces the number of required routing lines and interconnect resources, thereby reducing routing congestion and device complexity while maintaining transmission functionality through time-multiplexed data transfer.
3Adaptability or versatility
If more memory blocks are integrated on a single chip, then functionality is improved, but routing congestion and repair complexity increase
Solution Approach 1:
The patent implements a universal repair information storage block that can store and manage repair information for multiple memory blocks simultaneously. This universal storage structure allows a single repair controller to manage repairs across all memory blocks through serial transmission, reducing the need for separate repair circuits for each memory block. This multi-functional approach enables increased memory block integration while keeping repair complexity manageable through resource sharing and centralized control.
Data Source
AI summary
A memory repair device for detecting a fault cell in a memory and replacing it with a redundancy cell using a serial interface method is provided. The memory repair device include a repair information control block and at least one memory block including at least one memory. The repair information control block is configured to perform a built-in self-test (BIST) for each memory block, and when a fault cell is detected according to the BIST, receive and store repair information about the fault cell information. The memory block replaced the fault cell with a redundancy cell according to repair information loaded by the repair information control block at the time of operation of the memory. Data is transmitted and received between the repair information control block and the memory block using a serial interface.