Memory Controller Parity Mapping for Error Correction
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Solution Overview
Problem
Existing memory systems face challenges in performing error correction operations with optimal performance due to limitations in data bit and parity bit mapping, leading to inefficiencies in error detection and correction.
Innovation Solution
A memory system design that maps parity bits to different bit positions within corresponding data sets across multiple memory devices, allowing for improved error correction operations through a memory controller that performs parity checks and bit flipping to correct errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If parity bits are mapped to the same bit positions in all data sets, then the mapping structure is simple, but error detection capability is reduced
Solution Approach 1:
The patent applies asymmetry by mapping each parity bit to different bit positions across different data sets. Instead of using a symmetric mapping where the same bit position always corresponds to the same parity bit, the patent creates asymmetric mappings where the position of a parity bit varies depending on the data set being accessed. This asymmetry increases the likelihood that errors will manifest at different positions, improving error detection capability while maintaining a relatively simple mapping structure.
2Device complexity
If parity bits are distributed across fewer bit positions, then the mapping is simpler, but error correction performance deteriorates
Solution Approach 1:
The patent introduces an additional dimension to the mapping by incorporating both row and column indices in the mapping formula. Instead of mapping parity bits based on a single dimension (e.g., only bit position), the patent uses a two-dimensional approach where the mapping depends on both the row index (i) and column index (j) of the data bits. This dimensional expansion allows for better error correction performance by distributing parity information more effectively across the data sets without significantly increasing mapping complexity.
3Quantity of substance
If the same data bits are used for multiple parity bits, then storage efficiency is improved, but error detection reliability is reduced
Solution Approach 1:
The patent applies local quality by ensuring that each parity bit is associated with a unique combination of data bits based on its specific mapping position. Instead of having all parity bits share the same set of data bits (uniform quality), the patent creates local variations where each parity bit monitors a different subset of data bits. This is achieved through the mapping formula that incorporates both row and column indices, ensuring that parity bits at different positions protect different local regions of the data, thereby improving error detection reliability while maintaining storage efficiency.
Data Source
AI summary
A memory system is provided. The memory system includes: first memory devices; a second memory device; and a memory controller configured to control the plurality of first memory devices and the second memory device. Each of the first memory devices is configured to store a first data set including a first set of data bits in different bit positions, each of the bit positions corresponding to a burst order and a DQ. The second memory device is configured to store a second data set including parity bits for a plurality of first data sets, respectively stored in the plurality of first memory devices. A second set of data bits corresponding to a first parity bit of the parity bits are included in the plurality of first data sets, respectively, and at least two data bits of the second set of data bits have different bit positions.