Vertical Memory Channel Structures with Recessed Insulators
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing vertical memory devices face challenges in process yield due to misalignment and depth penetration of channel structures, which affect the operational characteristics and integration capabilities.
Innovation Solution
The memory device design includes a channel structure with multiple portions penetrating stacked gate layers and protrusions in recesses, along with a method of manufacturing that involves forming channel holes and recesses in alternating sacrificial layers, followed by replacing these with gate layers, to enhance alignment and prevent deep penetration into active gate layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel structures are formed to penetrate stacked gate layers in vertical memory devices, then integration capacity and memory capacity are improved, but misalignment and deep penetration into active gate layers occur reducing process yield
Solution Approach 1:
Recesses are formed in the interlayer insulating layers before the channel structure is deposited. This preliminary action creates a physical barrier that prevents the channel structure from penetrating too deeply into the active gate layers, thereby solving the misalignment and deep penetration problems while maintaining high integration capacity
Solution Approach 2:
The recesses in the interlayer insulating layers act as intermediary structures between the channel structure and the active gate layers. These recesses provide a controlled interface that limits the penetration depth of the channel structure, preventing direct contact with the active gate layers and thus improving process yield
2Volume of moving object
If the thickness of interlayer insulating layers is reduced to increase integration density, then device size is reduced, but alignment precision and operational characteristics deteriorate
Solution Approach 1:
Recesses are formed in the interlayer insulating layers before channel structure deposition. This preliminary structuring compensates for the reduced thickness of the interlayer insulating layers by creating physical boundaries that maintain alignment precision even when the overall layer thickness is reduced for higher integration density
3Quantity of substance
If more sacrificial layers are used to increase the number of gate layers, then memory capacity is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Recesses are formed in the interlayer insulating layers during the sacrificial layer formation process, before the final gate layers are created. This preliminary structuring simplifies subsequent manufacturing steps by pre-defining the channel structure boundaries, thereby reducing overall manufacturing difficulty despite using multiple sacrificial layers to increase memory capacity
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
Described is a memory device which may include a substrate; a first stack structure comprising a plurality of first gate layers and a plurality of first interlayer insulating layers alternately stacked on the substrate; a second stack structure comprising a plurality of second gate layers and a plurality of second interlayer insulating layers alternately stacked on the first stack structure; and a channel structure penetrating the first stack structure and the second stack structure, wherein the channel structure comprises a first portion in a first channel hole penetrating the first stack structure, a second portion in a second channel hole penetrating the second stack structure, and a first protrusion located in a first recess recessed into one layer of the plurality of first interlayer insulating layers from a side portion of the first channel hole.