Memory Controller Asymmetric Parity Mapping for Error Correction
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Solution Overview
Problem
Existing memory systems face challenges in performing error correction operations with optimal performance due to limitations in parity bit mapping and detection of error bits, leading to inefficiencies in data integrity and reliability.
Innovation Solution
A memory system design that includes a plurality of memory devices with parity bits stored at different bit positions across multiple memory devices, allowing for improved error detection and correction through a memory controller that performs parity checks and bit flipping operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity bits are stored at the same bit position in all memory devices, then the memory structure is simple and easy to implement, but the error detection and correction performance is limited
Solution Approach 1:
The patent applies asymmetry by storing parity bits at different bit positions across different memory devices rather than at the same position. Specifically, first parity bits are stored at first bit positions in first memory devices, while second parity bits are stored at second bit positions in second memory devices, where the bit positions differ. This asymmetric distribution improves error detection and correction performance while managing structural complexity.
2Reliability
If parity bits are distributed across multiple memory devices at different bit positions, then error detection capability is improved, but the complexity of parity bit mapping increases
Solution Approach 1:
The patent segments the parity bit storage function across multiple memory devices. First memory devices store first parity bits at first bit positions, while second memory devices store second parity bits at second bit positions. This segmentation distributes the error correction function across multiple components, improving data integrity while organizing the complexity into manageable segments.
Solution Approach 2:
The patent applies local quality by assigning different bit positions for parity bits in different memory devices. First memory devices use first bit positions for their parity bits, while second memory devices use second bit positions, creating locally optimized error detection capabilities in each device while contributing to overall system reliability.
3Productivity
If traditional parity check methods are used, then the implementation is simple, but the productivity of error correction operations is reduced
Solution Approach 1:
The patent applies preliminary action by pre-distributing parity bits to different memory devices at different bit positions before error occurrence. This preliminary asymmetric distribution enables faster error detection and correction operations, as the memory controller can more efficiently identify and correct errors without complex real-time calculations, thereby improving productivity.
Data Source
Figure 1
Figure 2A~2B
Figure 2C
AI summary
A memory system (20) is provided. The memory system (20) includes: first memory devices (200d_1-200d_n); a second memory device (200p); and a memory controller configured to control the plurality of first memory devices (200d_1-200d_n) and the second memory device (200p). Each of the first memory devices (200d_1-200d_n) is configured to store a first data set (Data) including a first set of data bits in different bit positions, each of the bit positions corresponding to a burst order and a DQ. The second memory device (200p) is configured to store a second data set (Parity) including parity bits for a plurality of first data sets (Data), respectively stored in the plurality of first memory devices (200d_1-200d_n). A second set of data bits corresponding to a first parity bit of the parity bits are included in the plurality of first data sets (Data), respectively, and at least two data bits of the second set of data bits have different bit positions.