Boron-Covered Semiconductor Pillars for VGAA Memory Density
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Solution Overview
Problem
The electrical performance of semiconductor structures in Vertical Gate All Around (VGAA) transistors used as access transistors in dynamic memory arrays is low, hindering higher integration density.
Innovation Solution
A semiconductor structure with discrete semiconductor pillars, a gate-all-around structure, and a boron-containing covering layer, including bridge gate structures, is designed to enhance electrical performance by increasing contact area and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If VGAA transistor structure is used to achieve higher integration density, then device size is reduced, but electrical performance deteriorates
Solution Approach 1:
The gate structure is designed to completely surround the semiconductor pillar in a nested configuration, with the gate-all-around structure enveloping the pillar and bridge gate structures extending through the pillar. This nested arrangement maximizes gate control over the channel while maintaining a compact footprint, thereby improving electrical performance without sacrificing integration density.
Solution Approach 2:
The invention transitions from planar gate control to three-dimensional gate-all-around control, where the gate structure extends in multiple directions (radially surrounding the pillar and vertically through the pillar). This dimensional change enhances gate control efficiency and electrical performance while maintaining the same device footprint, thus resolving the contradiction between integration density and electrical performance.
2Area of stationary object
If device size is reduced to increase integration density, then area is decreased, but contact area and capacitance are insufficient
Solution Approach 1:
The contact structure extends vertically along the semiconductor pillar rather than only horizontally at the surface. This vertical extension into the third dimension increases the contact area between the contact and the semiconductor pillar without increasing the lateral device footprint, thus maintaining high integration density while providing sufficient contact area and capacitance.
Solution Approach 2:
The contact structure is designed to wrap around and penetrate the semiconductor pillar, creating a nested configuration where the contact envelops the pillar. This nested arrangement maximizes the contact surface area within a compact volume, increasing capacitance and electrical contact quality without expanding the device area.
Data Source
AI summary
A semiconductor structure includes a base, a dielectric layer, a gate structure, and a covering layer. The base includes discrete semiconductor pillars. The semiconductor pillars are disposed at the top of the base and extend in a vertical direction. The dielectric layer covers the sidewall of the semiconductor pillar. The gate structure is disposed in the middle area of the semiconductor pillar. The gate structure includes a gate-all-around structure, the gate-all-around surrounding the semiconductor pillar. A first part of the dielectric layer is disposed between the gate structures and the semiconductor pillars. The covering layer covers the top of the semiconductor pillar and part of the sidewall close to the top. The material of the covering layer includes a boron-containing compound.