Semiconductor Failure Analysis With Fail I/O–Port Matching
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Solution Overview
Problem
In semiconductor devices with mixed logic and memory circuits, identifying the root cause of failures is inefficient due to the need for separate analysis methods and potential errors in physical coordinate calculations, leading to increased analysis time and man-hours.
Innovation Solution
A failure analysis device that stores fail bit data and failure diagnosis data, extracts fail I/O values, and determines matches between these values and memory connection port IDs to identify the failure part accurately, reducing the need for emission analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If emission analysis is performed to identify the failure part, then the accuracy of failure part identification is improved, but the analysis time and man-hours increase
Solution Approach 1:
The patent performs preliminary actions by extracting and storing fail I/O values and port ID values before actual failure analysis. The system pre-processes test results data to create a database of failure information, enabling rapid matching during actual analysis without requiring time-consuming emission analysis from scratch
Solution Approach 2:
The patent introduces an intermediary mechanism by using fail I/O values and port ID values as intermediaries to connect logic circuit test results with memory circuit failure data. These intermediary values serve as keys to match and correlate failure information across different circuits, eliminating the need for direct emission analysis
2Extent of automation
If distance calculation based on physical coordinates is used to identify failure parts, then the analysis process is automated, but errors occur due to rounding errors in coordinates during shrinking
Solution Approach 1:
The patent replaces the mechanical coordinate-based distance calculation system with a data-based matching system. Instead of relying on physical coordinates that suffer from rounding errors during device shrinking, the system uses fail I/O values and port ID values as digital identifiers to accurately match failure parts, eliminating coordinate precision issues
Solution Approach 2:
The patent changes the parameters used for failure part identification from physical coordinates to logical identifiers (fail I/O values and port ID values). This parameter transformation maintains automation while improving precision, as the new parameters are derived from test results data rather than geometric coordinates that are susceptible to rounding errors
3Measurement precision
If separate analysis methods are used for logic circuit and memory circuit, then the analysis accuracy for each circuit is maintained, but the overall analysis efficiency decreases
Solution Approach 1:
The patent merges the analysis processes for logic circuits and memory circuits by extracting and correlating failure information from both circuits using a unified approach. The system combines logic circuit test results with memory circuit failure data through fail I/O value matching, enabling simultaneous analysis of both circuits without sacrificing accuracy while significantly improving overall efficiency
Data Source
AI summary
A failure analysis device is for analyzing a failure of the semiconductor device equipped with a logic circuit and a memory circuit. It has a storage device and a processor. The storage device stores fail bit data obtained by testing the memory circuit and failure diagnosis data obtained by failure diagnosis for test results of the logic circuit. The processor extracts the fail I/O value from the fail bit data, extracts the data of the memory connection port which is the connection port to the memory circuit from among the estimated failure parts included in the failure diagnosis data, and determines match/not-match between the fail I/O value and the port ID value included in the data of the memory connection port.