Memory-Constrained Transaction Redundancy With Address Fault Detection
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Solution Overview
Problem
Existing safety mechanisms in memory-constrained systems, such as those used in automotive applications, do not effectively provide fail-safe operation and mixed criticality assurance, especially for memory subsystem safety.
Innovation Solution
The implementation of transaction redundancy circuitry in memory-constrained devices, which generates redundant transactions and transforms target addresses using error correction codes like Hamming or SECDED codes, ensuring data consistency and fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware safety mechanisms like lockstep hardware or error correction codes are used, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory access operation into separate segments: an original transaction path and a redundant transaction path. The redundancy circuitry creates a duplicate transaction that accesses a different memory location (second region) while the original transaction accesses the first memory location (first region). This segmentation allows safety verification through comparison without requiring complex hardware mechanisms at every stage.
Solution Approach 2:
The patent implements a copying mechanism where the redundancy circuitry creates a duplicate of the original transaction. The redundant transaction is a copy that includes the same command type and data bus information but targets a different memory region. This copying approach provides redundancy and fault detection capability while avoiding the need for more complex hardware safety mechanisms like lockstep processors or extensive error correction codes.
2Reliability
If redundant paths for system-level communications are provided, then reliability is improved, but memory resources are consumed
Solution Approach 1:
The patent introduces a new dimension for redundancy by accessing a different memory region (second region) rather than simply duplicating the same memory location. The redundancy circuitry transforms the target address to point to a second region of memory cells, creating spatial diversity in the redundancy approach. This allows the system to verify data integrity by comparing results from different memory regions without requiring additional memory resources beyond what is already allocated for normal operation.
Data Source
AI summary
Embodiments herein describe a methodology to achieve transaction redundancy in memory-constrained devices. In an example, an initiator circuit issues an original transaction that includes a memory access request and an address of a first region of memory cells. Transaction redundancy circuitry generates a redundant transaction having an address of a second region of the memory cells (e.g., at a fixed offset from the address of the original transaction). Address transformer circuitry transforms the initial target address of the original and/or redundant transaction to ensure that a bit fault in the initial address results in an incorrect transformed address that is separated from a desired address, which will result in a data mismatch when original data and redundant data are retrieved and compared. The initial target address may be transformed based on a Hamming, SECDED, CRC, and/or other code.