Memory Read-Path Parity Regeneration for Reliable Data Updates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory technologies face reliability issues due to data loss caused by various factors such as noise margin reduction, leakage currents, polarization degradation, and external disturbances, leading to errors that exceed the error correction capability of conventional error correction code engines.
Innovation Solution
An operating method for memories that activates a read command to correct errors during the read operation by regenerating parity using a write path, allowing for error correction and updating data in cells, including a read path, a write path, and an update command control unit to manage the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code engine is provided to correct errors in data, then data reliability is improved, but chip area increases due to increased size of error correction code engine
Solution Approach 1:
The patent combines the error correction function with the existing read operation by utilizing the read path to both read data and perform error correction. The error correction code engine is integrated into the read operation flow, where parity bits are read along with data and used to correct errors in-place within the same operational cycle, thereby improving data reliability without requiring a separate dedicated error correction processing unit that would increase chip area.
Solution Approach 2:
The read path is designed to serve multiple functions: it reads data from memory cells, reads parity bits for error correction, and performs error correction operations all within a single read operation cycle. This multi-functional approach allows the same hardware resources to handle both data retrieval and error correction, avoiding the need for additional dedicated error correction hardware and thus minimizing chip area expansion.
2Reliability
If error correction capability is increased to handle more error bits, then data reliability is improved, but the number of parities required increases leading to increased chip area
Solution Approach 1:
The system uses the parity bits that are read during the normal read operation to perform error correction on the data. The error correction process is self-contained within the read operation flow, where the parity information retrieved from memory cells is immediately utilized to correct errors in the read data without requiring external parity generation or additional parity storage resources. This self-service approach maintains data reliability while minimizing the quantity of parity-related resources.
3Reliability
If read operation is performed to output corrected data, then data reliability is improved through error correction, but additional operations are required increasing complexity of operation
Solution Approach 1:
The error correction operation is performed preliminarily within the read operation flow itself. Parity bits are read and error correction is executed during the same operational cycle as the data read, before the corrected data is output. This preliminary action approach integrates error correction into the read operation rather than requiring separate post-processing steps, thereby improving data reliability while managing operational complexity by performing correction early in the data retrieval process.
Data Source
AI summary
An operating method of a memory which can achieve high data reliability and a memory implementing the operating method are disclosed. In the event of errors in data stored in cells, the data is corrected using parity during a read operation. However, since the data with errors is stored in the cells, the data is corrected while the read operation is activated. This process ensures the reliability of the data.