PCRAM Cross-Point Architecture with Shared Word Lines
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Solution Overview
Problem
PCRAM devices face challenges in chip area efficiency due to large word line driver circuits and increased word line resistance, which affect overall chip performance and cost.
Innovation Solution
A novel cross-point architecture is introduced where memory cells form a centered squared lattice, reducing the number of word line driver sets and word line resistance by using common word lines and wider metal tracks, eliminating the need for costly immersion layers in the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional cross-point architecture is used, then memory cells can be arranged in a standard grid, but chip area increases and word line resistance increases due to large driver circuits
Solution Approach 1:
The patent applies asymmetry by displacing memory cells in alternating rows relative to each other, creating a staggered or offset pattern rather than a symmetric grid. This asymmetric arrangement allows word lines to be shared between adjacent rows, reducing the total number of word lines needed and thereby reducing word line resistance and driver circuit size, which directly addresses the contradiction between chip area and word line resistance.
2Adaptability or versatility
If more word line driver sets are used, then more memory rows can be accessed, but chip area and cost increase
Solution Approach 1:
The patent implements universality by designing word lines to serve multiple functions - each word line can be shared by multiple memory rows through the asymmetric displacement pattern. This multi-functionality allows the same word line infrastructure to access more memory rows without proportionally increasing the number of driver circuits, thereby improving memory access capability while controlling chip area and cost.
3Ease of manufacture
If standard fabrication process is used, then manufacturing is straightforward, but immersion layers are required which increase cost
Solution Approach 1:
The patent applies the extraction principle by removing the requirement for immersion layers from the fabrication process. The asymmetric cross-point architecture enables a fabrication approach that does not depend on immersion lithography, thereby simplifying the manufacturing process and reducing costs while maintaining the ability to manufacture the memory device with standard processes.
Data Source
AI summary
A cell array of a memory device includes: a first deck of memory cells arranged in a first row and a second row extending in a first horizontal direction and a plurality of columns extending in a second horizontal direction, wherein the memory cells in the second row in the first deck is displaced in the first horizontal direction with respect to the memory cells in the first row in the first deck; a first common word line metal track extending in the first horizontal direction, wherein both the memory cells in the first row and the memory cells in the second row are disposed on the first common word line metal track; and a plurality of first bit line metal tracks extending in the second horizontal direction, wherein each of the plurality of first bit line metal tracks is disposed on one of the first deck of memory cells.