3D Memory Cell Architecture for Substrate Area Optimization
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Solution Overview
Problem
Traditional integrated circuits face challenges due to the space-consuming memory cells with transistors on the semiconductor substrate, limiting the area available for complex control circuitry and increasing costs as the complexity of integrated circuits grows.
Innovation Solution
The integration of an array of memory cells above the semiconductor substrate without using a semiconductor layer, employing adjustable resistors and heating elements separated by dielectric layers, where data is stored by altering the resistivity of the resistors through heating, allowing for multi-bit storage without the need for transistors at the substrate surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional memory cells with transistors are used on the semiconductor substrate, then memory storage capability is achieved, but the surface area available for control circuitry is reduced
Solution Approach 1:
The patent moves memory cells from the two-dimensional substrate surface to a three-dimensional configuration using suspended structures and vias that extend vertically through dielectric layers. This dimensional transition allows memory cells to occupy vertical space rather than horizontal substrate area, freeing up surface area for control circuitry while maintaining memory storage capability.
Solution Approach 2:
The patent introduces dielectric layers and suspended structures as intermediary elements between the substrate and memory cells. These intermediaries support the memory cells in a lifted configuration, enabling electrical connection via vias while isolating the memory cells from direct substrate contact, thus preserving substrate area for control functions.
2Adaptability or versatility
If more transistors are added to increase control circuitry complexity, then control functionality is improved, but the substrate area required increases
Solution Approach 1:
By implementing memory cells in a vertical suspended architecture rather than planar substrate integration, the patent enables control circuitry to be densely packed on the substrate surface without competing for space with memory cell transistors. The memory cells occupy the vertical dimension through suspended structures, while control circuitry utilizes the horizontal substrate plane.
3Ease of manufacture
If memory cells are formed at the substrate surface, then manufacturing process is simplified, but the footprint of the integrated circuit increases
Solution Approach 1:
The patent achieves compact footprint by transitioning memory cell implementation from horizontal substrate surface to vertical suspended structures. The memory cells extend upward through dielectric layers using vias and suspended platforms, converting horizontal footprint expansion into vertical dimension utilization, thereby reducing the overall integrated circuit footprint.
4Quantity of substance
If traditional floating gate memory cells are used, then data storage is achieved, but the area per memory cell is large
Solution Approach 1:
The patent reduces area per memory cell by implementing a vertical suspended architecture where memory elements extend through multiple dielectric layers in the vertical dimension. This three-dimensional configuration packs more memory cells into a smaller horizontal footprint, decreasing the area required per memory cell while maintaining data storage capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables increased surface area for control circuitry, reduces costs, and enhances memory capacity without increasing the semiconductor substrate footprint, allowing for more complex processing and memory density in a smaller form factor.
Implementation Method 1
The heating element is separated from the adjustable resistor by a second dielectric layer and is configured to write data to the adjustable resistor by heating the adjustable resistor to alter its structure and thus its resistivity
Implementation Method 2
The first thin film layer is chromium silicon having a first concentration of silicon and the second thin film layer is chromium silicon having a second concentration of silicon different than the first concentration. The first thin film layer mixes with the second thin film layer to alter the resistance of the adjustable resistor when heat is applied to the adjustable resistor
Data Source
AI summary
An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.