Digital Storage TRIZ Cases

Adjustable PMOS loads and equalization transistors cancel sensing offset in MRAM, improving read margin, speed, and read reliability.

Back-bias voltage normalizes clock delay steps across PVT variation, improving memory timing reliability with low power and compact circuitry.

Using the search key as a memory address, this TCAM cuts comparison logic, power use, and update latency while enabling single-cycle lookup.

Additional write circuitry shifts and inverts data across bit-line sections, enabling complex logic in computational memory arrays.

Two amplification paths let the comparator adapt to slow and fast operation, improving internal clock phase and frequency alignment.

A shift-register phase mixer changes input clock weighting in discrete fine-delay steps to shorten DDLL locking time while preserving phase accuracy.

Multiple internal reference voltages let the buffer amplify input signals faster while avoiding external voltage sources and complex circuitry.

Additional output transition circuitry speeds latch voltage switching, cutting memory access delay caused by sequential cross-coupled NAND gates.

Dynamic strobe delay adjustment keeps data and strobe phases aligned under PVT variations for stable, accurate high-speed reception.

An always-on master latch preserves stored data while the slave latch powers down, cutting circuit power without data corruption.

Resistive non-volatile memory refreshes FPGA configuration data to resist radiation errors with lower complexity and power.

Clock-controlled transistor paths and delay balancing cut propagation delay in memory level shifters for faster voltage translation.

In-array sensing circuitry calculates and compares error codes across memory banks, reducing external circuitry and processing time.

Masked refresh clock edges let a capacitive digital isolator avoid data-path conflicts, noise, and excess power while preserving signal integrity.

Hybrid FinFET SRAM cells use elevated gate voltage control to pass full VDD in FPGA configuration memory while reducing leakage and die area.

Back-bias voltage tunes clock duty cycle to offset PVT timing variation, improving memory data reliability and stable transmission.

A ratioless write port lets ultra-low VDD SRAM overwrite data without oversized write transistors, improving Boolean write efficiency.

Configurable memory block I/O circuits carry high-bandwidth data outside general routing fabric, easing congestion and preserving operating frequency.

A folded register and multiplexer layout cuts parasitic capacitance and clock routing size, enabling faster and more uniform latency shifting.

Isolating one output driver leg enables cleaner duty cycle measurement by reducing load reflections and distortion during signal adjustment.

A DFE feedback circuit with tunable latch references cuts PAM4 DDR inter-symbol interference and improves memory signal detection.

Extending selected clock pulses lets memory latches and row drivers avoid clock-data race conditions without hurting access time or cycle time.

Fixes internal clock delay to a target value without a continuous reference clock, stabilizing pulse width and improving memory read reliability.

Negative-feedback Op-amp row driving cuts row switch resistance error in RRAM crossbar arrays without larger switches or added parasitic R/C.

Additional write circuitry shifts and inverts data across bit-line sections, enabling XOR and XNOR in computational memory arrays with lower power.

Background duty cycle calibration updates clock trim values only when needed, preserving timing windows across voltage and temperature changes.

Multiple light beads, a paraboloid mirror, and a textured lens improve automotive indicator light uniformity while sealing the cavity.

A dedicated bank-to-bank bus routes data between memory banks on the shortest path, reducing external bus use, transfer time, and power in PIM.

Mode-switching between multiphase and dual-edge clocks cuts timing deviation at high frequency while lowering power in semiconductor memory.

A single-stack clock driver generates two-pulse memory timing with less area and clock power while tolerating input load variation.

A two-stage programming pulse heats and switches MLU cells with one current path, reducing synchronization complexity and voltage stress.

Integrated pulldown circuits let resistive memory compare data and find min or max values inline, improving processing efficiency and power use.

Earlier and later clock phases stabilize scan-path inputs in flip-flops, cutting hold failures and extra delay circuitry at low voltage.

Programmable trim circuits correct input buffer transition-voltage mismatches to align setup and hold timing and improve memory data reliability.

Clock frequency checking lets an SMD circuit adjust delay only when needed, cutting delay units, current consumption, and circuit size.

Multiple pre-generated reference voltage levels let a buffer settle faster and amplify differential or single-ended signals precisely.

Selective replica delay activates only when strobe toggles, aligning data timing while limiting current spikes and power noise.

Resistive memory sets and resets voltage relationships between signal lines, making programmable array logic more flexible without added hardware cost.

Phase blending interpolates between coarse delay stages to prevent non-monotonic clock timing and improve programmable delay consistency.

Feed-forward equalization on previously received signals removes post-cursor reflections and preserves eye margin in high-speed semiconductor links.

Josephson phase-based torque switches a magnetic memory cell state while avoiding CMOS leakage and static power dissipation.

Multiple temperature-code latches update refresh control only after a match, improving self-refresh stability and current consumption consistency.

A ring of clocked inverters generates quadrature clock signals with lower delay, smaller area, and faster recovery from common clock levels.

Repeaters segment long GIO lines, amplify and level-shift data, and cut current use while limiting distortion and data loss in semiconductor I/O transfer.

Phase-difference detection and delayed input selection stabilize data transfer between external and internal clock domains.

Segmented buffer channels let eight DIMMs share one memory channel, expanding capacity while maintaining signal integrity and transfer speed.

Using phased sampling timing signals, this case shows how memory circuits capture valid data windows to raise transfer speed without excessive area growth.

Incoming strobe edges drive an adaptive gating window that suppresses overhead transitions while tolerating chip drift and clock jitter.

Automatic clock-toggle detection powers down LPDDR2 clock input buffers during stable periods, then re-enables them quickly to cut standby power.

Adjusting high or low pulse duration from previous bit patterns improves bit identification margins in high-speed memory links.