Input Buffer Trimming for Transition Voltage Alignment
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Solution Overview
Problem
Integrated circuit memory devices face issues with data reliability due to variability in transition voltages across input buffers, leading to misalignment in setup and hold times, which can cause errors in high-speed and low-voltage applications.
Innovation Solution
The implementation of trim circuitry with serially-coupled transistors and mismatch detection operations to adjust the transition voltage of input buffers to a target voltage, ensuring alignment and improving reliability by determining and adjusting the transition voltage based on detected offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If memory operations are suspended during power-down or standby state, then power consumption is reduced, but unintended leakage current occurs through circuitry suspended in high voltage states
Solution Approach 1:
The patent applies preliminary action by performing mismatch detection and trim adjustment operations before the memory enters power-down or standby state. The input buffers are calibrated to have matched transition voltages while still in normal operation, so that when power is reduced, the buffers maintain proper timing alignment even with leakage current present. This preliminary calibration prevents timing errors that would otherwise occur during low-power states.
2Reliability
If input buffers are used to condition received data signals, then data reliability is improved, but variability in transition voltages causes misalignment in setup and hold times
Solution Approach 1:
The patent applies local quality by individually calibrating each input buffer's transition voltage through mismatch detection and trim adjustment. Rather than relying on uniform manufacturing characteristics, each buffer is locally adjusted to have its transition voltage matched to a reference, compensating for process variations. This local customization ensures that setup and hold times are properly aligned for each buffer despite manufacturing variability.
Solution Approach 2:
The patent applies parameter changes by adjusting the transition voltage parameter of each input buffer through trim circuitry. The mismatch detection operation identifies the actual transition voltage of each buffer, and the trim adjustment modifies this parameter to match the target value. This parameter adjustment compensates for manufacturing variations and ensures consistent timing alignment across all input buffers.
3Manufacturing precision
If trim circuitry is added to adjust transition voltages, then transition voltage alignment is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by performing the mismatch detection and trim adjustment operations during an initialization phase before normal operation begins. The calibration is done once when the device is powered up or entered into a specific calibration mode, and the trim settings are stored for use during normal operation. This approach avoids the need for continuous complex adjustment circuitry during normal data processing.
Solution Approach 2:
The patent applies self-service by implementing an automated mismatch detection and trim adjustment process that calibrates the input buffers without requiring external intervention. The system uses its own internal resources to detect mismatches and apply corrections, storing the trim settings for future use. This self-calibration capability reduces the need for external testing and adjustment equipment.
Data Source
AI summary
Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.