Programmable Array Logic Using Resistive Memory Voltage Setting
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Solution Overview
Problem
Current programmable array logic devices lack the flexibility and performance needed while maintaining cost-effectiveness, as they are limited in their ability to dynamically adjust signal voltage levels.
Innovation Solution
The integration of resistive memory to isolate and set voltage relationships between signal lines, allowing for dynamic adjustment of voltage levels through programmable AND and OR gates, enhancing flexibility and performance without increasing hardware costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional programmable array logic is used, then hardware cost is reduced, but flexibility and performance are limited due to inability to dynamically adjust voltage levels
Solution Approach 1:
The patent applies the dynamics principle by introducing resistive memory cells that can be dynamically programmed to different resistance states, enabling the logic circuit to change its voltage relationships and logic functions after manufacturing. This allows the same hardware structure to adapt to different logical operations by adjusting the resistance values of memory cells, thereby improving flexibility without proportionally increasing hardware complexity.
Solution Approach 2:
The patent utilizes parameter changes by varying the resistance values of memory cells to control voltage division ratios between signal lines. By programming memory cells to different resistance states, the circuit can dynamically adjust voltage levels and implement different logic functions using the same physical hardware, resolving the contradiction between flexibility and hardware complexity.
2Productivity
If traditional programmable array logic is used, then hardware cost is reduced, but performance is limited due to static voltage relationships
Solution Approach 1:
The patent implements dynamics by enabling reconfigurable voltage relationships through programmable resistive memory. The memory cells can be set to different resistance values to create various voltage division ratios, allowing the circuit to optimize its performance for different logic operations dynamically, thereby improving productivity without requiring multiple dedicated hardware circuits for each function.
Solution Approach 2:
The patent applies universality by designing a single hardware structure that can perform multiple logic functions through programmable memory cells. The same AND/OR gate structure can implement different logical operations by changing the resistance values of memory cells, making the hardware multi-functional and improving performance without proportional increases in hardware complexity.
3Adaptability or versatility
If resistive memory is integrated to enable dynamic voltage adjustment, then flexibility and performance are improved, but hardware cost may increase
Solution Approach 1:
The patent applies merging by combining the logic gate functionality with resistive memory cells into a single integrated structure. The memory cells are embedded within the logic circuit pathways, serving dual purposes as both storage elements and voltage control elements. This integration reduces the total component count and hardware cost compared to having separate logic gates and programmable voltage control circuits.
Solution Approach 2:
The patent utilizes universality by making the resistive memory cells serve multiple functions: they act as both data storage elements and voltage division control elements. This multi-functionality reduces the need for additional dedicated voltage control hardware, thereby improving flexibility while minimizing increases in hardware cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the programmable array logic's flexibility and performance by enabling repeated setting and resetting of voltage relationships, reducing hardware costs and enhancing operational efficiency.
Implementation Method 1
the first resistive memory is configured to isolate the coupled first signal line from the coupled second signal line, and set a relationship between a voltage level of the corresponding first signal line and a voltage level of the corresponding second signal line
Implementation Method 2
the second resistive memory is configured to isolate the coupled third signal line from the coupled fourth signal line, and set a relationship between a voltage level of the corresponding third signal line and a voltage level of the corresponding fourth signal line
Data Source
AI summary
A programmable array logic includes a plurality of first signal lines, a plurality of second signal lines coupled to input terminals of a plurality of programmable AND gates, a plurality of first control units coupled to the first signal lines and second signal lines, a plurality of third signal lines coupled to output terminals of the programmable AND gates, a plurality of fourth signal lines coupled to input terminals of a plurality of programmable OR gates, and a plurality of second control units coupled to the third signal lines and the fourth signal lines. Each of the first control units has at least a first resistive memory for setting voltage level relationship between the first signal lines and the second signal lines. Each of second control units has a second resistive memory for setting voltage level relationship between the third signal lines and the fourth signal lines.