Quadrature Clock Ring Divider With Fast Self-Oscillation

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Solution Overview

Problem

Conventional quadrant divider circuits for semiconductor memories are cumbersome due to complex circuits, have long path delays, and slow recovery times from common clock levels, and occupy significant area.

Innovation Solution

A novel quadrant divider circuit design with clocked inverter circuits coupled in a ring configuration, utilizing fewer inverter circuits to generate quadrature clock signals with reduced delay and area, and achieving self-oscillation quickly upon changes in input clock levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional quadrant divider circuits are used, then reliable multiphase clock signal generation is achieved, but device complexity increases and area occupation increases

Engineering Contradiction:

Improvemultiphase clock signal generationVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple inverter circuits into a compact ring configuration where inverters are coupled in series to form a closed loop. This integration reduces the overall circuit complexity while maintaining the functionality of generating multiphase clock signals, directly addressing the contradiction between reliability and device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The ring configuration nests the inverter circuits within a compact structure where each inverter is embedded in the loop, sharing common nodes and signals. This nesting approach reduces area occupation while preserving the circuit's ability to generate reliable multiphase clock signals.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Reliability

If conventional quadrant divider circuits are used, then sufficient clock signal processing is achieved, but path delay increases

Engineering Contradiction:

Improveclock signal processingVSAvoidpath delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the clock signal processing into distinct phases by using the ring configuration of inverters, where each inverter stage processes a portion of the signal transformation. This segmentation allows for optimized signal propagation through each stage, reducing the overall path delay while maintaining reliable clock signal processing.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The ring configuration enables continuous operation of the clock signal processing without interruption, as the signal continuously circulates through the inverter loop. This continuous action eliminates idle time between processing stages, reducing path delay while ensuring reliable clock signal generation.

Inventive Principle:

Principle #20Continuity of useful action

3Reliability

If conventional quadrant divider circuits are used, then complete clock level recovery is achieved, but recovery time increases

Engineering Contradiction:

Improveclock level recoveryVSAvoidrecovery time

Core Design Contradiction:

ReliabilityVSDuration of action of moving object

Solution Approach 1:

The ring configuration of inverters is designed to automatically initiate the clock level recovery process as soon as the input clock levels change. The interconnected nature of the ring structure prepositions the circuit states to enable immediate response, reducing recovery time while ensuring complete clock level recovery is achieved.

Inventive Principle:

Principle #10Preliminary action

4Reliability

If conventional quadrant divider circuits are used, then proper phase relationship is achieved, but area occupation increases

Engineering Contradiction:

Improvephase relationshipVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the phase generation functionality into a single compact ring structure, where multiple phase relationships are generated simultaneously through the sequential stages of the inverter loop. This consolidation achieves proper phase relationships while minimizing the area occupation compared to separate phase generation circuits.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The ring configuration utilizes a topological arrangement where the circuit elements are connected in a closed loop, effectively using the dimensional arrangement of the ring to pack the circuit more efficiently. This dimensional change allows for proper phase relationship generation in a reduced area compared to linear or distributed configurations.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10636461B2Apparatuses and methods for providing multiphase clock signals

Publication Date: 2020.04.28 MICRON TECHNOLOGY INC

AI summary

Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second clock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.