Signal Receiving Circuit With Feed-Forward Equalization for Reflections
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Solution Overview
Problem
High-speed semiconductor systems face challenges in maintaining signal integrity due to reduced time margins and decreased eye or valid windows for data transmission, exacerbated by signal reflections in transmission lines, which existing technologies struggle to address effectively.
Innovation Solution
A signal receiving circuit is designed with buffers, sampling circuits, and equalizers that generate and synchronize amplification and sampling clock signals to amplify and sample received signals, and perform equalization operations based on previously inputted signals, using a feed-forward equalization method to compensate for post-cursor reflections without relying on sampling circuit outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the clock signal is increased to perform data communication at high speed, then the operating speed of the semiconductor apparatus is improved, but the time margin required for transmitting and receiving data is reduced
Solution Approach 1:
The equalizer performs equalization operations on previously-inputted received signals before they are sampled. By preparing equalized signals in advance (preliminary action), the circuit can quickly provide clean signal levels during the reduced time margin window, enabling high-speed operation without sacrificing the necessary time for signal conditioning.
2Speed
If the frequency of the clock signal is increased to perform data communication at high speed, then the operating speed of the semiconductor apparatus is improved, but the eye or valid window of the transmitted or received data is decreased
Solution Approach 1:
The equalizer changes voltage levels of equalization signals based on previously-inputted received signals before the current sampling moment. This preliminary equalization prepares the signal with optimal voltage levels in advance, ensuring that when the data is sampled during the reduced eye window, the signal quality is already optimized for high-speed operation.
3Manufacturing precision
If a decision feedback equalizer is used to compensate for post-cursor component caused by reflection, then the eye or valid window of the signal is increased, but the circuit complexity increases
Solution Approach 1:
The equalizer performs equalization operations on previously-inputted received signals before current sampling. By using feed-forward equalization on past signals rather than decision feedback requiring current sample decisions, the circuit achieves post-cursor compensation with reduced complexity, as it does not require the full decision feedback loop architecture.
Data Source
AI summary
A signal receiving circuit includes a buffer, a sampling circuit, and an equalizer. The buffer generates first and second amplified signals by amplifying a currently-inputted received signal in synchronization with an amplification clock signal. The sampling circuit generates an output signal by sampling the first and second amplified signals in synchronization with a sampling clock signal. The equalizer changes voltage levels of the first and second amplified signals based on third and fourth amplified signals which are generated from a previously-inputted received signal in synchronization with the amplification clock signal.