Computational Memory Write Circuits for Cross-Bit-Line Logic
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Solution Overview
Problem
Current memory cells can only perform simple logical functions when connected to the same read bit line, limiting their ability to execute more complex logical operations across multiple memory cells.
Innovation Solution
Incorporating additional write processing circuitry into a processing array with computational memory cells, allowing data shifting between bit line sections and enabling more complex logical functions through read/write logic and data inversion control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory cells are connected to the same read bit line to perform logical functions, then logical computation capability is improved, but the complexity of circuitry required to facilitate complex logical functions increases
Solution Approach 1:
The memory cells perform logical computations using their own storage elements (flip-flops) and existing read/write circuitry. The computational capability arises from the self-organizing behavior of the memory array during read operations, where the interaction of multiple memory cells on a shared bit line naturally produces logical functions without requiring external computational units.
Solution Approach 2:
The memory cells are designed to serve dual purposes: data storage and logical computation. The same memory structure that stores binary data also performs logical operations when multiple cells are accessed simultaneously through shared bit lines, eliminating the need for separate computational hardware.
2Adaptability or versatility
If additional write processing circuitry is added to enable data shifting between bit line sections, then the ability to perform complex logical functions is improved, but the device complexity increases
Solution Approach 1:
The memory array is divided into multiple sections or banks, each with its own set of bit lines. Write processing circuitry is implemented in a modular fashion, with each section having independent write control logic. This segmentation allows data to be shifted between sections while keeping the complexity of individual write processing units manageable.
Solution Approach 2:
Write processing circuitry acts as an intermediary between the control logic and the memory cells. This intermediate layer handles the complex tasks of data shifting, inversion, and coordination between bit line sections, shielding the rest of the system from the complexity of these operations while enabling sophisticated data manipulation capabilities.
Data Source
AI summary
A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.