Clock Phase Detection Circuit for Stable Domain Crossing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices face challenges in performing stable data input/output operations due to phase differences between external and internal clocks, leading to synchronization issues during domain crossing operations.
Innovation Solution
Incorporating a detection signal generation circuit to detect phase differences and generate delayed input signals, and an output enable signal generation circuit to synchronize data output with either the internal clock or its inverted signal, thereby controlling the input time of signals for stable domain crossing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an internal clock generation circuit using PLL or DLL is used to generate the internal clock, then the internal clock can be generated with a stable frequency, but a phase difference (skew) occurs between the external clock and the internal clock causing synchronization issues during domain crossing operations
Solution Approach 1:
The patent applies preliminary action by detecting the phase difference between the external clock and internal clock before the domain crossing operation occurs. The detection signal generation circuit measures the phase skew in advance, and the delay control circuit pre-adjusts the timing of the input signal based on this detected phase difference, ensuring proper synchronization is established before data transfer begins.
Solution Approach 2:
The patent implements feedback by using the detection signal generation circuit to continuously monitor the phase difference between clocks and feed this information back to the delay control circuit. The delay control circuit adjusts the timing of input signals based on this feedback, creating a closed-loop system that maintains proper synchronization despite variations in clock phases.
2Device complexity
If the input signal timing is not adjusted according to the phase difference, then the circuit operation is simple, but synchronization errors occur during domain crossing between external and internal clocks
Solution Approach 1:
The patent introduces an intermediary mechanism - the detection signal generation circuit and delay control circuit - that mediates between the external clock domain and internal clock domain. This intermediary detects the phase relationship and adjusts signal timing accordingly, enabling reliable domain crossing without requiring complex redesign of the entire clock synchronization system.
3Measurement precision
If delay control signals are counted to control the input time of the input signal, then accurate timing control is achieved, but the device complexity increases
Solution Approach 1:
The patent applies parameter changes by adjusting the delay amount of the input signal based on the detected phase difference parameter. The delay control circuit modifies the timing parameter of the input signal dynamically, allowing precise control of signal input time while using a relatively simple delay adjustment mechanism rather than a completely complex timing control system.
Data Source
AI summary
A semiconductor device includes a detection signal generation circuit generating a detection signal by detecting a phase difference of an input signal and an internal clock, and generating delayed input signals by delaying the input signal. The semiconductor device further includes an output enable signal generation circuit outputting an output enable signal by selecting one of the delayed input signals in response to the detection signal and latching the selected one of the delayed input signals in synchronization with the internal clock. The output enable signal may initiate a data transfer operation.