Pulse-Stretching Clock Circuitry for Memory Race Conditions
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Solution Overview
Problem
Conventional memory circuitry fails to address the race condition between the input clock signal and the input data signal during read/write operations, particularly when the input clock signal does not change polarity, leading to inefficiencies in memory access.
Innovation Solution
The implementation of pulse stretcher circuitry, which includes first and second pulse stretching circuits, is used to extend the pulse width of clock signals, ensuring that the address row driver is turned off before the arrival of new clock or data signals, thereby resolving the race condition through the use of enable signals to control phase 2 latches and column multiplexer circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the input clock signal fails to change polarity during read/write operations, then the race condition between clock and data signals occurs, but the address row driver cannot be turned off in time
Solution Approach 1:
The pulse stretcher circuit extends the pulse width of the clock signal in advance before it reaches the address row driver. By preliminarily stretching the clock pulse duration, the system ensures that the driver has sufficient time to complete its operation and turn off before the next clock edge arrives, thereby preventing race conditions without extending the overall memory access time.
Solution Approach 2:
The clock signal path is segmented into multiple stages: the original clock signal is separated into a stretched clock signal path (through the pulse stretcher) and a non-stretched path. This segmentation allows different parts of the system to receive clock signals with different pulse widths, enabling the address row driver to operate with extended timing while other parts maintain original timing constraints.
2Reliability
If the pulse width of clock signals is extended to resolve race condition, then the address row driver can be turned off before new signals arrive, but the cycle time may be impacted
Solution Approach 1:
The pulse stretching is applied locally only to specific clock signals that control the address row driver, rather than extending all clock signals throughout the system. This localized application of pulse stretching improves the hold margin for the critical path (address row driver timing) without unnecessarily extending the cycle time for other operations that do not require additional timing margin.
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.