Sampling Circuit Timing Windows for Faster Memory Data Transfer
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently transmitting data between the device and an external controller due to limitations in synchronization signal handling, which affects data transmission speed.
Innovation Solution
A sampling circuit comprising a first timing determination circuit, a second timing determination circuit, and a sampling data output circuit, which determine and output data timings based on distinct sampling timing signals, allowing for effective data sampling and arrangement between rising edges of these signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single sampling timing signal is used for data transmission, then the device complexity is reduced, but the data transmission speed is limited
Solution Approach 1:
The patent divides the data transmission process into multiple segments by using multiple sampling timing signals (first sampling timing signal and second sampling timing signal) with different phases. Each sampling circuit samples data during specific time intervals defined by these signals, enabling parallel data transmission paths that increase overall transmission speed while maintaining manageable circuit complexity through structured segmentation
Solution Approach 2:
The patent introduces a temporal dimension to data transmission by utilizing multiple sampling timing signals with different phases. Instead of transmitting data sequentially through a single sampling path, the system transmits multiple data values simultaneously at different time points within a clock cycle, effectively adding a time-based dimension to the transmission process that increases speed without proportionally increasing complexity
2Speed
If multiple sampling timing signals are used to increase transmission speed, then the data transmission speed improves, but the area efficiency is reduced
Solution Approach 1:
The patent designs sampling circuits that can be uniformly replicated and applied across multiple data transmission paths. Each sampling circuit uses the same structural design but operates with different sampling timing signals, allowing the system to achieve high transmission speed through parallelism while minimizing area overhead by avoiding redundant circuit variations
Solution Approach 2:
The patent employs sampling circuits that hold and maintain sampled data values during specific time intervals defined by the sampling timing signals. By carefully controlling when data is sampled, held, and transferred, the system maximizes the utilization of each sampling circuit's capacity over time, effectively recovering and reusing circuit resources across multiple data transmission operations within the same area
3Productivity
If data is sampled between rising edges of sampling timing signals, then the data transmission efficiency is improved, but the timing determination complexity increases
Solution Approach 1:
The patent uses periodic sampling timing signals with defined phases to systematically sample data at regular intervals. The first and second sampling timing signals operate in a periodic manner with specific phase relationships, allowing timing determination circuits to use simple phase-based logic rather than complex arbitrary timing calculations, thereby improving efficiency while controlling complexity
Solution Approach 2:
The patent introduces phase information as an intermediary element that mediates between the multiple sampling timing signals and the data sampling process. By using phase differences between signals as a controlling parameter, the timing determination circuits can efficiently coordinate multiple sampling operations without requiring complex direct timing analysis, thus improving data transmission efficiency while keeping the timing determination logic manageable
Data Source
AI summary
A sampling circuit may include a first timing determination circuit, a second timing determination circuit, and a sampling data output circuit. The first timing determination circuit may determine a first timing of sampling data in response to a first sampling timing signal. The second timing determination circuit may determine a second timing of the sampling data in response to a second sampling timing signal. The sampling data output circuit may output the sampling data having effective data values of the data between the first timing and the second timing in response to outputs from the first and second timing determination circuits.