Configurable Memory I/O Circuits for High-Bandwidth FPGA Routing
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Solution Overview
Problem
The increasing demand for high data bandwidth in programmable logic devices leads to routing congestion in the integrated circuit's routing fabric, degrading the maximum operating frequency due to the strain on programmable interconnects used for memory operations.
Innovation Solution
Implementing memory blocks with configurable input and output circuits that act as intermediaries between the memory and the routing fabric, allowing for flexible port configurations and operation modes to manage high bandwidth operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory blocks are connected using programmable interconnects in the general routing fabric, then data input and output bandwidth capabilities can be increased, but routing congestion increases and maximum operating frequency degrades
Solution Approach 1:
The patent introduces dedicated memory interconnect structures as intermediary elements between memory blocks and the general routing fabric. These specialized interconnects act as mediators that handle high-bandwidth memory traffic separately from general logic routing, thereby increasing data bandwidth capability while preventing routing congestion in the general fabric.
Solution Approach 2:
The patent segments the routing fabric into dedicated memory interconnect paths and general logic routing paths. By dividing the routing resources into separate domains, memory traffic is isolated from general logic traffic, allowing high bandwidth operations without degrading the overall routing fabric and maintaining high operating frequencies.
2Productivity
If memory blocks are connected using programmable interconnects in the general routing fabric, then data input and output bandwidth capabilities can be increased, but maximum operating frequency degrades
Solution Approach 1:
Dedicated memory interconnect structures serve as intermediary pathways that bypass the general routing fabric for memory access. This mediation allows high-speed memory operations to occur through optimized paths with fewer logic stages, thereby increasing data bandwidth while maintaining the maximum operating frequency of the programmable logic device.
Solution Approach 2:
By segmenting the interconnect architecture into dedicated memory paths and general logic paths, the patent creates separate timing domains. The dedicated memory interconnects are optimized for high-speed memory access with minimized logic stages, allowing high operating frequencies to be maintained even as data bandwidth capability increases through additional memory blocks.
3Adaptability or versatility
If configurable input and output circuits are implemented in memory blocks, then flexible port configurations and operation modes are achieved, but device complexity increases
Solution Approach 1:
The patent implements universal configurable input and output circuits within memory blocks that can perform multiple functions through configuration controls. These circuits can be programmed to operate in different modes (e.g., different port configurations, different data widths, different timing modes) without requiring physically different circuitry, thereby achieving high adaptability while managing device complexity through reuse of the same hardware resources.
Data Source
AI summary
An integrated circuit may include integrated memory that is formed from a chain of memory blocks. Each memory block may have configurable input and output circuits. The configurable input and output circuits may be interposed between memory circuitry such as a memory array from circuitry external to the memory circuitry. The configurable input and output circuits may have upstream and downstream memory block connection ports. In such a way, configurable input and output circuits in a first memory block may pass control and address signals and data to configurable input and output circuits in a second memory block. By using the configurable input and output circuits, the integrated memory in the integrated circuit may operate to accommodate large bandwidth flows without using the general routing fabric of the integrated circuit.