Phase-Blended Variable Delay Line for Monotonic Clock Timing
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Solution Overview
Problem
Traditional computer memory delay lines exhibit non-monotonic behavior due to mismatches between coarse and fine delay stages, leading to inconsistent timing signals.
Innovation Solution
A monotonic variable delay line is implemented using a plurality of coarse delay circuits and a phase blender circuit, which receives input clock signals and control signals to generate phase signals, interpolating the coarse delay and presenting an output clock signal that mitigates mismatches between delay stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional capacitive load switching is used to produce fine delay independent of coarse delay, then fine delay can be generated, but non-monotonic behavior occurs due to mismatches between coarse and fine delay stages
Solution Approach 1:
The patent merges the coarse delay stage and fine delay stage into a unified delay line structure where the fine delay is derived from the coarse delay through phase blending. The phase blender circuit combines multiple phase-shifted versions of the coarse delay signal to generate the fine delay, ensuring that both stages are correlated and work together to produce monotonic delay behavior.
Solution Approach 2:
The patent implements dynamic phase blending where the fine delay is continuously adjusted based on the coarse delay value. The phase blender dynamically interpolates between different phase-shifted signals to achieve precise delay control while maintaining monotonicity. This dynamic adjustment ensures that as the coarse delay changes, the fine delay adapts proportionally to maintain overall monotonic behavior.
2Loss of time
If coarse delay stages are used to provide delay, then coarse delay can be generated, but mismatches between coarse delay stages cause non-monotonic behavior in timing signals
Solution Approach 1:
The patent implements a feedback mechanism where the output of the coarse delay stage is fed into the phase blender, which then generates the fine delay based on the actual coarse delay value. This feedback loop ensures that any variations or mismatches in the coarse delay stages are compensated for in the fine delay generation, maintaining timing consistency and monotonic behavior.
Solution Approach 2:
The patent segments the delay line into multiple parallel paths with different phase shifts, where each path processes the coarse delay signal independently. The phase blender then combines these segmented paths to generate the fine delay. This segmentation allows for better control and compensation of mismatches in individual coarse delay stages.
3Adaptability or versatility
If traditional delay line architecture is used with uncorrelated coarse and fine delay stages, then delay functionality is provided, but non-monotonicity results from lack of correlation between stages
Solution Approach 1:
The patent makes the delay line dynamically correlated by deriving the fine delay from the coarse delay through phase blending. The system adaptively adjusts the fine delay based on the actual coarse delay value, ensuring that changes in one stage are reflected in the other stage. This dynamic correlation maintains monotonic behavior while preserving programmability.
Solution Approach 2:
The patent changes the relationship between coarse and fine delay from independent parameters to correlated parameters. The fine delay is now a function of the coarse delay parameter, specifically through phase blending of the coarse delay signal. This parameter transformation ensures that monotonicity is maintained while allowing flexible programmability of the overall delay.
Data Source
AI summary
An apparatus includes a plurality of coarse delay circuits and a phase blender circuit. The coarse delay circuits may be configured to (i) receive an input clock signal, (ii) receive a plurality of control signals and (iii) generate a first phase signal and a second phase signal. The phase blender circuit may be configured to (i) receive the first phase signal and the second phase signal, (ii) receive a phase control signal, (iii) step between stages implemented by the coarse delay circuits and (iv) present an output clock signal. The phase blender circuit may mitigate a mismatch between the stages of the coarse delay circuits by interpolating an amount of coarse delay provided by the coarse delay circuits.