Memory Bank Transfer Bus for Low-Power Parallel Data Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face inefficiencies in data transfer between banks, requiring external buses and consuming significant power and time, especially in processing-in-memory (PIM) implementations where internal bus usage is limited.
Innovation Solution
Implementing a bank-to-bank transfer (BBT) bus separate from the internal bus to facilitate parallel, optimized data transfer between memory banks, minimizing power consumption and transfer time by selecting the shortest path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If data transfer between memory banks uses external buses, then data transfer is possible, but power consumption increases and transfer time increases
Solution Approach 1:
The patent divides the memory system into multiple banks (first bank, second bank, third bank, fourth bank) with dedicated point-to-point transfer paths between them. This segmentation eliminates the need for a shared external bus, reducing power consumption and transfer time by enabling direct, isolated data routes between specific banks.
Solution Approach 2:
The patent introduces an intermediary controller that manages and coordinates data transfers between memory banks through dedicated transfer paths. This intermediary enables efficient bank-to-bank transfers without requiring external buses, reducing both power consumption and transfer time while maintaining system coherence.
2Loss of time
If data transfer between memory banks uses external buses, then data transfer is possible, but transfer time increases
Solution Approach 1:
The patent implements segmented, dedicated transfer paths between specific memory banks (e.g., first bank to second bank, third bank to fourth bank). This segmentation enables parallel data transfers without contention, significantly reducing transfer time compared to shared external buses while maintaining manageable internal complexity.
Solution Approach 2:
The patent transitions from a traditional hierarchical bus structure to a mesh-like point-to-point connection topology. This dimensional change in the data transfer architecture enables simultaneous multi-bank operations, reducing transfer time by eliminating bus arbitration delays and contention.
3Productivity
If processing-in-memory operations are implemented, then processing performance improves, but data transfer efficiency between banks becomes limited
Solution Approach 1:
The patent merges processing capabilities directly into the memory banks, enabling processing-in-memory operations. Simultaneously, it combines this with dedicated bank-to-bank transfer paths, ensuring that data required for processing can be efficiently transferred between banks without relying on slower external buses, thus maintaining high processing performance.
Solution Approach 2:
The patent enables continuous data transfer between memory banks through dedicated transfer paths, ensuring that processing-in-memory operations can proceed without interruption. This continuity eliminates the start-stop nature of shared bus transfers, maintaining high productivity by ensuring data is always available when needed for processing operations.
Data Source
AI summary
The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.