Computational Memory Write Circuits for Bit-Line Data Shifting
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Solution Overview
Problem
Existing memory cells can only perform simple logical functions when connected to the same read bit line, limiting the complexity of operations that can be performed across multiple memory cells.
Innovation Solution
A processing array with computational memory cells and additional write processing circuitry that allows data shifting and inversion between bit line sections, enabling more complex logical functions by connecting read data storage outputs to adjacent bit line sections and using multiplexers to select write data sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory cells are connected to the same read bit line to perform simple logical functions, then the logical function capability is improved, but the complexity of logical functions that can be performed is limited
Solution Approach 1:
The patent makes memory cells multi-functional by enabling them to perform both storage and complex logical operations (XOR, XNOR, AND, OR, NOT) within the same cell structure. The dual-port SRAM cell design allows data to be read from one port and written to another port simultaneously, enabling the cell to function as both memory storage and logic processing unit, thereby increasing adaptability without proportionally increasing device complexity
Solution Approach 2:
The patent merges the storage function and logic processing function into a single integrated memory cell structure. By combining the read and write ports of the SRAM cell and connecting them to shared bit lines, the design eliminates the need for separate storage and processing circuits, reducing overall system complexity while enhancing logical function capability
2Adaptability or versatility
If additional write processing circuitry is added to enable data shifting between bit line sections, then the complexity of logical functions is improved, but the device complexity increases
Solution Approach 1:
The additional write processing circuitry is designed to be multi-functional, serving both as data shifting mechanism between bit line sections and as part of the logic processing unit. The same circuit elements that enable data movement are also utilized for logical operations, ensuring that the increase in device complexity is justified by proportional gains in logical function capability
Solution Approach 2:
The patent divides the memory array into multiple bit line sections, each capable of independent operation. This segmentation allows complex logical functions to be broken down into simpler sub-functions that can be executed in parallel across different sections, reducing the complexity burden on any single circuit element while achieving high overall logical function complexity
3Quantity of substance
If traditional SRAM cells are used for data storage, then the storage capability is improved, but the data processing capability and power consumption are limited
Solution Approach 1:
The dual-port SRAM cell is designed to perform multiple functions simultaneously: data storage, data processing (XOR, XNOR, AND, OR, NOT operations), and data movement between bit line sections. This eliminates the need for separate processing circuits, thereby enhancing data processing capability while maintaining storage capability and reducing overall power consumption
Solution Approach 2:
The memory cell performs data processing operations on the data stored within it without requiring external processing units. The cell uses its own internal circuitry to execute logical operations directly on the stored data, enabling the storage element to serve its own processing needs and improving overall system productivity
Data Source
AI summary
A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.