Memory Clock Delay Circuit for Stable Pulse Width Control
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Solution Overview
Problem
Existing memory devices face challenges in accurately controlling the delay between input and output clock signals without a reference clock signal, leading to irregular pulse widths and reduced data valid windows during read operations.
Innovation Solution
A delay control circuit that generates an internal clock by delaying an external clock and adjusts the output delay to a target value, using a digital delay control circuit, clock distribution circuit, phase detector, low-pass filter, and delay code generator to synchronize the internal clock with the external clock, ensuring consistent pulse widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference clock signal is used to control delay, then the output delay can be accurately fixed at target delay, but the device complexity increases due to requiring continuous reference clock input
Solution Approach 1:
The patent extracts the delay measurement function from the continuous reference clock signal path. Instead of requiring a continuous reference clock, the system only samples delay information at specific moments (when input clock edges occur), separating the delay measurement function from continuous clocking requirements.
Solution Approach 2:
The patent introduces delay information as an intermediary parameter that carries delay measurement data without requiring continuous reference clock presence. This intermediary allows the system to maintain accurate delay control while operating without continuous reference clock input.
2Device complexity
If delay control is implemented without reference clock signal, then the device complexity is reduced, but the output delay becomes unstable and pulse widths become irregular
Solution Approach 1:
The patent implements feedback by continuously monitoring the delay information generated from input and output clock signals. The delay control signal generator uses this feedback to dynamically adjust delay control signals, ensuring the output delay remains stable at the target delay even without continuous reference clock input.
Solution Approach 2:
The system performs self-correction by generating delay information from its own output clock signal and using this information to adjust its own delay control. This self-service mechanism maintains output delay stability without requiring external reference clock intervention.
3Adaptability or versatility
If the input clock signal is not continuously provided, then the adaptability to power management is improved, but the delay control accuracy deteriorates
Solution Approach 1:
The patent uses periodic sampling of delay information at each input clock edge occurrence. This periodic measurement approach allows the system to maintain accurate delay control during active periods while allowing the input clock to be suspended during inactive periods, achieving both power management adaptability and measurement precision.
Solution Approach 2:
The system prepares delay measurement circuits to be ready for immediate measurement when the input clock signal arrives. This preliminary preparation ensures that accurate delay information can be captured at the moment the clock signal becomes available, maintaining measurement precision despite intermittent operation.
Data Source
AI summary
A delay control circuit, which may be included in a memory device, includes a delayed signal generator configured to generate an output signal by delaying an input signal in response to a delay control signal and a delay information generator configured to generate delay information indicating an output delay between the input signal and the output signal. The delay control circuit also includes a delay control signal generator configured to, based on a result of a comparison between target delay information indicating a target delay between the input signal and the output signal and based on the delay information, generate the delay control signal for controlling the output delay and fix the output delay at the target delay in response to the delay control signal.