SRAM Cell With Ratioless Write Port for Ultra-Low VDD Writes

The patent divides the SRAM cell into separate functional components: storage transistors (maintaining data) and write transistors (performing write operations). By segmenting the write path from the storage latch, the write transistors can be optimized independently without increasing overall cell complexity. The write operation is segmented into controlled phases using write word line signals that isolate the write path from the storage latch during writing.

The patent prepares the write path in advance by pre-charging write bit lines and positioning write transistors in a ready state before the actual write operation. The write word line is activated beforehand to enable the write path, and the write transistors are positioned to connect the write bit lines to the storage latch only when needed, avoiding the need for continuously strong write transistors.

The patent makes the write transistor strength dynamic rather than static. Write transistors are sized normally but are activated only when write word line signals are applied. The effective strength of write transistors is dynamically adjusted through timing control and signal sequencing, allowing successful writes without requiring permanently oversized write transistors that would increase area and manufacturing cost.

The patent changes the operating parameters of the write operation by controlling the timing and sequence of write word line signals. Instead of relying on fixed transistor strength ratios, the write success is achieved by adjusting temporal parameters (signal timing, pulse width, sequencing) that enable the write path to temporarily overpower the storage latch only during the write window, reducing the need for larger write transistors.

The patent designs the SRAM cell to serve multiple functions: it can store data traditionally and also perform Boolean operations (AND, OR, NAND, NOR, XOR, XNOR) using the same cell structure. The write port is designed with universal control signals that can initiate either traditional write operations or Boolean computation operations, eliminating the need for separate circuitry for different operations and improving efficiency.

The SRAM cell performs Boolean operations using its own internal transistors and logic elements without requiring external computation circuits. The cell serves itself by utilizing the interaction between write transistors and storage transistors to naturally compute Boolean functions based on the states of write bit lines and storage nodes, eliminating the bandwidth bottleneck between separate computation and storage devices.