Single-Stack Clock Driver for Double-Pumped Memory Timing
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Solution Overview
Problem
Conventional memory sub-systems face limitations due to large load constraints and area inefficiencies in clock driver topologies, which affect the slew rate and power consumption in memory operations.
Innovation Solution
The implementation of a single stack clock driver in clock generating circuitry for double-pumped memory applications, reducing the total driver fin count and simplifying logic to generate a negative global timing pulse (NGTP) for single, dual, and multi-port memory systems, using a single transistor as the clock driver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock driver topology is used, then the memory sub-system can drive large load to generate global timing pulse, but the area consumption and device complexity increase significantly
Solution Approach 1:
The clock driver is divided into two separate drivers: a first clock driver that generates the global timing pulse (GTP) and a second clock driver that generates the inverted GTP. This segmentation allows each driver to be optimized for its specific function, reducing the area required compared to a single large driver handling both functions.
Solution Approach 2:
The first and second clock drivers are designed to be substantially identical in structure, allowing one driver design to serve multiple functions (generating both GTP and inverted GTP). This universality reduces design complexity and allows for efficient area utilization through replication of a compact, optimized driver unit.
2Reliability
If conventional clock driver topology is used, then the memory sub-system can generate global timing pulse, but the slew rate of derived clocks deteriorates due to cascading effect
Solution Approach 1:
By separating the clock driving functions into two dedicated drivers, each driver can be optimized to drive its specific load without the cascading effects that occur when a single driver attempts to drive multiple derived clocks. This segmentation preserves the slew rate of derived clocks by eliminating the cascading degradation.
3Reliability
If conventional clock driver topology is used, then the memory sub-system can operate with standard clock signals, but power consumption increases
Solution Approach 1:
The clock driving function is segmented into two specialized drivers, each optimized for its specific timing pulse generation. This segmentation allows for more efficient power utilization compared to a single driver operating at higher power levels to handle all clock generation tasks.
Data Source
AI summary
Various implementations described herein refer to an integrated circuit having a first pulse generator and a second pulse generator. The first pulse generator generates a first clock pulse for a two pulse sequence based on one or more input signals. The second pulse generator is coupled to the first pulse generator and generates a second clock pulse for the two pulse sequence based on the one or more input signals. The second pulse generator has a single stack clock driver that provides an output clock signal having the two pulse sequence.