Flip-Flop Clock Phasing for Scan Hold-Time and Low-Voltage Operation
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Solution Overview
Problem
Sequential circuits face hold-time violations and challenges in low voltage operation, particularly in scan mode, due to insufficient delay between flip-flops, leading to data corruption and the need for additional delay circuits that increase power and area consumption.
Innovation Solution
The implementation of a flip-flop circuit with a selection circuit, memory element, and clock circuit that generates both an earlier and later version of the clock signal, allowing the selection circuit to stabilize input signals during read operations, and using a non-inverting enable circuit to prevent inadvertent copying between master and slave portions, reducing the need for additional delay circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional delay circuits are added to prevent hold-time violations, then hold time adherence is improved, but power consumption and area increase
Solution Approach 1:
The patent combines the delay function with the existing flip-flop structure by using the clock signal itself to provide the necessary delay through phased clocking. The selection circuit is controlled by an earlier phase of the clock signal while the memory element is controlled by a later phase, effectively merging the delay function into the clock distribution network rather than adding separate delay circuits.
Solution Approach 2:
The patent introduces an intermediary clock signal phase distribution mechanism that mediates between the launch and capture flip-flops. By using an earlier clock phase for the selection circuit and a later clock phase for the memory element, the system creates a time buffer without requiring additional delay elements, thus avoiding the power and area penalties of traditional delay circuits.
2Reliability
If additional delay circuits are added to prevent hold-time violations, then hold time adherence is improved, but device area increases
Solution Approach 1:
The patent merges the delay function with the existing flip-flop structure by using the clock signal itself to provide the necessary delay through phased clocking. The selection circuit is controlled by an earlier phase of the clock signal while the memory element is controlled by a later phase, effectively merging the delay function into the clock distribution network rather than adding separate delay circuits.
Solution Approach 2:
The clock signal serves multiple functions: it triggers the flip-flop operation, provides timing reference for the selection circuit, and inherently provides the delay mechanism through its phased distribution. This multi-functionality eliminates the need for dedicated delay circuits, reducing area overhead.
3Use of energy by moving object
If hold time requirements are reduced, then low voltage operation is improved, but data stability during read operations becomes compromised
Solution Approach 1:
The patent applies preliminary action by stabilizing the input signal to the memory element before the read operation commences. The selection circuit, controlled by the earlier clock phase, completes its selection and stabilizes the output before the memory element (controlled by the later clock phase) begins its read operation, ensuring data stability without requiring excessive hold time.
Solution Approach 2:
The patent uses periodic clock signal phases to rhythmically control the selection circuit and memory element. The periodic nature of the clock ensures that the selection circuit consistently completes its operation before the memory element reads, providing reliable data stability through regular timing cycles rather than relying on long hold times.
Data Source
AI summary
According to one general aspect, an apparatus may include a flip-flop circuit. The flip-flop circuit may include a selection circuit, a memory element circuit, a clock circuit. The selection circuit to select, as the selected input signal, between at least two input signals. The memory element circuit synchronously controlled by a clock signal, and configured to store the selected input signal. The clock circuit configured to output, at least, an earlier version of the clock signal and a later version of the clock signal. The selection circuit is configured to be synchronously controlled, at least in part, by the earlier version of the clock signal such that the selected input signal is held stable when being read by the memory element circuit.