Multiphase Clock Generation for Low-Power Timing Accuracy
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in reducing timing deviations of clock signals, which can lead to erroneous operations, especially at higher frequencies, while also requiring reduced power consumption, particularly in low power applications.
Innovation Solution
A semiconductor device with a clock dividing circuit that provides internal clock signals with reduced timing deviation by operating in different modes, adjusting clock frequencies and phases, and using multiphase clock signals to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If circuits are used to adjust clock signal timing to reduce timing deviation, then timing accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock frequency adjustment by switching between different clock domains (first clock domain with higher frequency and second clock domain with lower frequency) based on operational requirements. This dynamic adaptation allows the system to use higher frequencies only when necessary for performance, reducing timing deviations during critical operations while consuming less power during normal operations when lower frequencies suffice.
Solution Approach 2:
The system changes the clock frequency parameter by selecting between different clock domains. The first clock domain provides higher frequency clocks for operations requiring precise timing, while the second clock domain provides lower frequency clocks for power-saving operations. This parameter change enables the system to balance timing accuracy and power consumption based on real-time needs.
2Speed
If higher frequency clock signals are used for faster operation, then speed is improved, but timing deviations increase causing erroneous operation
Solution Approach 1:
The patent dynamically switches between clock domains based on the operational state. During operations where timing accuracy is critical, the system uses the first clock domain with higher frequency but with controlled duty cycles. During less critical operations, it transitions to the second clock domain with lower frequency, thereby maintaining reliability while achieving high speed when needed.
Solution Approach 2:
The system monitors operational requirements and adjusts clock frequency selection accordingly. By implementing control logic that determines when to switch between clock domains based on operation type and timing requirements, the system provides feedback-driven clock management that maintains timing accuracy during high-speed operations.
Data Source
AI summary
Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.