Folded Register Latency Shifter for Low-Capacitance Clock Routing
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Solution Overview
Problem
Conventional latency shifters in memory devices face issues with large parasitic capacitances and speed differences due to undesirably large gate and wiring capacitances, as well as inefficient clock distribution, which affect the delay and propagation of signals.
Innovation Solution
The proposed solution involves a latency shifter with a folded layout of registers and multiplexers, where registers are arranged in series along two crossing paths, allowing for efficient signal propagation with reduced parasitic capacitance and optimized clock distribution, enabling high-speed operation by aligning the input and output registers and using logic gates to control clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional latency shifters use multiple lines of flip-flops with different lengths to provide variable delay, then the desired delay amounts can be achieved, but gate and wiring capacitances at the contact point become undesirably large
Solution Approach 1:
The patent transforms the conventional linear arrangement of flip-flops into a folded topology where the signal path bends back on itself. This dimensional reconfiguration allows the input and output contact points to be positioned adjacent to each other rather than at opposite ends of a long line, dramatically reducing the wiring capacitance while maintaining the required signal delay through the folded path.
Solution Approach 2:
The patent merges the input and output contact points into the same physical location or adjacent positions by folding the signal path back. This consolidation eliminates the need for long interconnect wires between input and output, reducing parasitic capacitance while preserving the delay function through the folded flip-flop chain.
2Ease of manufacture
If conventional latency shifters arrange drivers of clocks for respective flip-flop groups in traditional layouts, then clock distribution is simple, but parasitic capacitances increase charge/discharge currents undesirably
Solution Approach 1:
The clock distribution network is reconfigured to follow the folded topology of the flip-flop chains. Clock drivers are positioned and routed to match the folded layout, allowing compact clock tree structures that reduce wire lengths and parasitic capacitances, thereby lowering charge/discharge currents while maintaining synchronized clock distribution across all flip-flop groups.
3Adaptability or versatility
If conventional latency shifters pass signals through different numbers of selectors depending on flip-flop selection, then variable delay is achieved, but speed differences occur based on how much delay is selected
Solution Approach 1:
The patent implements uniform selector stages distributed along the folded flip-flop path, where each stage has identical structural characteristics. This ensures that regardless of how many stages are activated to achieve the desired delay, each signal path segment maintains consistent speed characteristics, eliminating the speed variations that occur in conventional designs where signal paths of different lengths inherently have different propagation speeds.
Data Source
AI summary
Examples described herein include command latency shifters which may include a plurality of registers arranged in a folded topology.