3D Memory Channel Hole Formation via Wafer Bonding
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Solution Overview
Problem
The challenge in semiconductor technology is the difficulty in forming deep channel holes in 3D memory devices due to the increasing complexity and cost of etching processes as feature sizes shrink, leading to limitations in memory density and channel hole aspect ratio.
Innovation Solution
A method involving the formation of a device wafer with an epitaxial layer and channel holes, followed by bonding with connecting wafers to create a joint channel hole structure with a large aspect ratio and controlled thickness, using hybrid bonding to enhance structural strength and simplify the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If etching processes are used to form channel holes in 3D memory devices with increasing oxide/nitride layers, then memory density can be improved, but the etching process complexity and cost increase significantly
Solution Approach 1:
The patent divides the formation of deep channel holes into multiple stages by creating alternating layers of sacrificial material (e.g., silicon nitride) and dielectric material (e.g., silicon oxide). This segmentation allows each etching step to target only specific layers, reducing overall process complexity while achieving the desired memory density through multiple shallower etching operations rather than one deep etching process
2Length of moving object
If conventional etching processes are used to form deep channel holes, then channel hole depth can be increased, but the aspect ratio control becomes difficult and process cost increases
Solution Approach 1:
The patent introduces sacrificial layers (e.g., silicon nitride) as intermediary structures that facilitate controlled etching. These sacrificial layers act as mediators that define the etching depth and aspect ratio by being selectively removed in controlled steps, enabling precise aspect ratio control while achieving the required channel hole depth without direct conventional etching
3Quantity of substance
If feature sizes of memory cells are reduced to increase density, then memory capacity improves, but planar process techniques become challenging and costly
Solution Approach 1:
The patent transitions from planar memory cell structures to three-dimensional vertical structures by forming channel holes that extend deeply into the substrate with alternating layers. This dimensional change from 2D planar to 3D vertical architecture allows continued scaling of memory capacity while avoiding the manufacturing challenges and costs associated with further reducing planar feature sizes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves channel mobility and string current in 3D memory devices, speeds up deep channel hole development, reduces process complexity, and lowers costs by forming dual-deck or multi-deck channel hole structures with robust inter-deck connections.
Implementation Method 1
forming an epitaxial layer on a bottom of the first channel hole
Implementation Method 2
forming a first tunneling layer on a surface of the first storage layer for tunneling electronic charges
Data Source
AI summary
Embodiments of a method for forming a three-dimensional (3D) memory devices are disclosed. The method can comprise forming a device wafer including: forming a first channel hole penetrating a first alternating layer stack of a device wafer, forming an epitaxial layer on a bottom of the first channel hole, and forming a first channel layer on a sidewall of the first channel hole. The method can further comprise forming at least one connecting wafer, each connecting wafer including a second channel hole penetrating a second alternating layer stack without an epitaxial layer on a bottom of the second channel hole; and bonding the at least one connecting wafer and the device wafer, such that a second channel layer on a sidewall of the second channel hole in each connecting wafer is electrically connected with the first channel layer in the device wafer.