3D Memory Array Channel Composition for Mobility and Process Damage
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in achieving high device performance and reducing manufacturing defects, particularly in three-dimensional memory arrays, due to limitations in carrier mobility and process damage during processing.
Innovation Solution
A three-dimensional memory array is designed with vertically stacked memory cells, each incorporating a thin film transistor (TFT) featuring a ferroelectric gate dielectric and an oxide semiconductor channel region with varying indium concentrations, optimizing carrier mobility and reducing electron scattering and process damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory array with vertically stacked memory cells is designed, then device density is increased, but manufacturing complexity and process damage increase
Solution Approach 1:
The channel region is segmented into multiple distinct regions (first channel region, second channel region, third channel region) with different semiconductor element concentrations. This segmentation allows each region to be optimized for specific functions: the first region near the gate electrode provides high carrier mobility, the second region reduces electron scattering, and the third region minimizes process damage, thereby enabling high-density 3D memory structures while managing manufacturing complexity
Solution Approach 2:
Different regions of the channel are assigned different local qualities through varying semiconductor element concentrations. The first channel region has a first concentration optimized for carrier mobility near the gate, the second channel region has a second concentration optimized for reducing electron scattering in the middle section, and the third channel region has a third concentration optimized for reducing process damage at the exposed surface. This local quality differentiation resolves the contradiction by enabling high-density stacking while controlling manufacturing complexity through localized optimization
2Reliability
If carrier mobility is increased through material composition optimization, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The invention changes the parameter of semiconductor element concentration across different channel regions to optimize device performance. By establishing a gradient where the first channel region has a first concentration for high carrier mobility, the second channel region has a second concentration for reduced electron scattering, and the third channel region has a third concentration for reduced process damage, the patent achieves improved device performance while managing manufacturing precision through systematic parameter variation rather than uniform composition
3Speed
If electron scattering is reduced through channel region optimization, then carrier mobility increases, but device complexity increases
Solution Approach 1:
The second channel region is specifically optimized with a second semiconductor element concentration that differs from the first and third regions, creating a localized zone that reduces electron scattering. This local quality optimization improves carrier mobility and speed without requiring complete redesign of the entire device structure, thereby managing device complexity while achieving the performance improvement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances carrier mobility and reduces manufacturing defects, leading to improved device performance and increased density in semiconductor memory arrays.
Implementation Method 1
optimizing carrier mobility
Implementation Method 2
featuring a ferroelectric gate dielectric
Data Source
AI summary
A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.