3D Memory Channel Structure for Lower Parasitic Coupling
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Solution Overview
Problem
Three-dimensional (3D) memory devices face limitations in scalability and performance due to parasitic capacitive coupling between adjacent memory cells, which degrades their operational efficiency and increases storage costs.
Innovation Solution
A 3D memory architecture is developed with a stack of alternately stacked dielectric and conductive layers, featuring a second dielectric layer with a dielectric constant greater than or equal to 3.9 and a blocking layer with specific thickness and surface profiles, which reduces parasitic capacitive coupling by increasing the equivalent oxide thickness and alleviating voltage drops between conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar memory structure is used, then manufacturing is simpler, but scalability is limited and memory capacity cannot be increased
Solution Approach 1:
The patent transitions from planar (2D) memory structure to three-dimensional (3D) stacked structure, where multiple dielectric layers and conductive layers are stacked vertically to form a multi-layer memory device. This dimensional change enables increased memory capacity by utilizing vertical space while maintaining compatibility with existing manufacturing processes.
2Productivity
If dielectric layer thickness is reduced to increase capacity, then memory density increases, but parasitic capacitive coupling between adjacent cells increases
Solution Approach 1:
The patent employs a composite dielectric structure consisting of a first dielectric layer with lower dielectric constant and a second dielectric layer with higher dielectric constant. This composite structure allows optimization of both capacitance and parasitic coupling characteristics, enabling reduced thickness while maintaining performance by strategically placing high-k material in specific regions.
Solution Approach 2:
The patent applies different dielectric materials with different properties to different regions of the structure. The second dielectric layer with higher dielectric constant is positioned in specific locations to enhance capacitance where needed, while the first dielectric layer with lower dielectric constant is used in regions where reducing parasitic coupling is critical, achieving local optimization of electrical characteristics.
3Reliability
If conventional blocking layer is used, then manufacturing is simpler, but voltage drops between conductive layers occur and reliability decreases
Solution Approach 1:
The blocking layer is designed with non-uniform thickness, where the first blocking portion has greater thickness than the second blocking portion. This local variation in thickness provides enhanced voltage blocking capability at critical interfaces while maintaining overall structural integrity, preventing voltage drops between adjacent conductive layers without requiring complete redesign of the blocking layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and performance of 3D memory devices by reducing parasitic capacitive coupling and leakage, thereby improving reading, writing, and data holding capabilities while reducing storage costs.
Implementation Method 1
The second dielectric layer can have a dielectric constant greater than or equal to 3.9
Implementation Method 2
parasitic capacitive coupling between adjacent memory cells
Data Source
AI summary
The disclosure provides a three-dimensional (3D) memory, a method of fabricating a 3D memory and a memory system. The 3D memory can include a stack including alternately stacked first dielectric layers and conductive layers, and a channel structure extending through the stack and including a second dielectric layer and a blocking layer disposed in this order from outside to inside. The second dielectric layer can have a dielectric constant greater than or equal to 3.9.