Solid-State Devices TRIZ Cases

Composite dielectric, metal, and IR-blocking layers suppress light leakage in BLC pixels, improving thermal background measurement accuracy.

A segmented panel with linked signal lines drives both sides in sync, preserving transparency and preventing left-right image reversal.

Tapered circuit holes self-align micro LEDs and reflect emitted light, improving placement accuracy, brightness, and display yield.

An intermediate electrode bridges spaced pixel contacts to improve electrical connection and light output without excessive electrode complexity.

Subwavelength PDMS nanostructures cut reflection and widen light incidence angles, boosting image sensor sensitivity and quantum efficiency.

Asymmetric fin widths and active region placement balance n-type and p-type FinFET drive strength while improving current resistance and circuit performance.

An integrated mesh-and-opening mask removes separate connecting members, cutting OLED deposition steps, cost, and visible dark lines.

Inline inspection and magnetic pickup let micro-LED transfer systems raise speed without sacrificing yield by screening out defective assemblies.

A split polarizing layer under the encapsulation substrate shortens camera light paths, reducing distortion without widening the display.

A variable-thickness reflective sidewall helps miniaturized LEDs keep over 90% reflectivity and strong light extraction despite inclined chip surfaces.

A buried doped region under a surface terminal enables compact bidirectional ESD protection with lower on-resistance and symmetric triggering.

Multi-depth pixel separation regions scatter incident light to reduce non-uniform color mixing and improve phase difference detection.

Light-blocking wall layers between adjacent sensing elements stop reflected-light crosstalk and improve signal accuracy with simpler fabrication.

N-type and P-type layers around DTI block interface leakage without polysilicon, preserving optical sensitivity and improving CMOS image sensor SNR.

Two-step liner opening and trench isolation control sacrificial-layer etching in 3D NAND, preventing core-area overetch and collapse.

Column-stacked pins over a shared source region help multi-gate IC cells save footprint and fit pin routing across CPP and M1 pitch constraints.

Individually controlled heating pixels and LEDs create local substrate temperature zones to stabilize grating etch depth during ion beam processing.

A bottom coating with thickness gradients and ridge lines creates a stable contact plane that prevents chip tilt and preserves emission direction.

Etched holes in the quantum well interrupt edge leakage paths, stabilizing luminance and improving external quantum efficiency.

A buried oxide and trench isolation layout protects the floating diffusion region while cutting crosstalk, dark current, and fixed picture noise.

A buried doped region under separated terminals creates a compact P-N-P path that lowers on-resistance and supports bidirectional ESD triggering.

A mesh reflective electrode and stress relieving layer improve LED current spreading, light extraction, and thermal stress control.

A partial light adjusting layer scatters edge-concentrated light to improve emission uniformity and light output in compact LEDs.

An inverted taper insulator between micro-LED electrodes limits shorts during placement, preserving alignment tolerance and connection stability.

A dual-layer nitride-oxide etch stop stack improves MRAM via stopping control while limiting dielectric damage and current leakage.

A two-layer refractive index structure suppresses silicon surface reflection across wide wavelengths, improving sensor sensitivity and reducing flare.

Implanted PN-junction vertical channels replace etched transfer gates to cut white pixels, reduce surface defects, and preserve blooming control.

Lateral conductive films and reflective side surfaces shrink side-view LEDs while improving heat dissipation and light extraction.

Different AlGaN thicknesses create dual-Vt GaN transistors that cut static current while preserving over-drive voltage and noise immunity.

A monolithic process forms multi-wavelength micro-LEDs and TFTs on one substrate, cutting transfer complexity, cost, and scaling barriers.

Applying out-of-range voltage or current conditions the dielectric layer to raise capacitance without thinning it or increasing leakage current.

Interlayer and multi-level decoders simplify memristor access in 3D stacked synaptic modules while reducing area and preserving cell characteristics.

Vertical stacking of light-emitting element layers raises element density to improve display luminance and resolution within limited sub-pixel area.

A trap-site stamp and matched carrier wells enable parallel microLED transfer with precise positioning, higher yield, and reusable devices.

Segmented through holes in the gate insulation layer shield the TFT active layer during metal etching while preserving source-drain conduction.

Overlapping contact holes cut non-light area and improve common electrode connection in oxide-semiconductor display panels.

A multilayer transflective reflector hides the sensor opening by matching reflectance and color across opaque and transmissive regions.

A wiring-layer isolation part uses low and high refractive index regions to reflect oblique light and limit pixel-to-pixel color mixing.

Spacers and a dual buried gate keep floating diffusion away from gate walls, cutting trap-site noise and parasitic capacitance.

A vertical gate with a spacer and insulation layer suppresses potential humps and improves charge transfer in miniaturized image sensor pixels.

By stacking the touch signal line under the common electrode in the opening area, this array panel improves aperture ratio and reduces visual defects.

A recessed inorganic stack and filling layer enable single-layer lap-joint routing across the bending area, cutting resistance and improving contact.

Current control across same-color LED chips boosts outdoor LED film brightness, improves heat dissipation, and enables day-night dimming.

A high-k second dielectric layer and profiled blocking layer reduce parasitic coupling, leakage, and voltage drop in 3D memory.

By removing direct N-type diffusion at the I/O pin, this ESD circuit blocks forward leakage and avoids deep N-well isolation cost.

A through-hole between substrates reflects peak-intensity light multiple times to boost front intensity and improve display luminance.

Multiple SiOx layers plus an annealed silicon oxynitride cap limit hydrogen diffusion into oxide TFT active layers and reduce short-circuit risk.

Multiple current-mirror detection paths tailor clamp trigger speed and strength to improve ESD current discharge and reduce voltage differential.

Grafted polymer brushes tune the photoresist-substrate interface in EUV lithography to improve adhesion, limit residue, and protect fine patterns.

An integrated N-type layer and thermal cleaning approach helps miniaturized display emitters keep light efficiency while lowering process risk.