Array Substrate Through-Hole Layout for TFT Etch Protection
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Solution Overview
Problem
In TFTs with the gate, source, and drain electrodes disposed in the same layer, the metal etching solution used for forming these electrodes corrodes the active layer, affecting electrical conduction and reducing device performance and yield rates.
Innovation Solution
An array substrate design featuring a gate electrode insulation layer with specific through hole configurations that shields regions of the active layer from the etching solution, ensuring normal electrical connection between the source and drain electrodes and the active layer, thereby preventing corrosion and enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wet etching process is used to form metal electrodes, then ease of manufacture is improved, but the active layer is corroded affecting electrical conduction
Solution Approach 1:
The gate electrode insulation layer is divided into multiple regions with different transparency to etching solution: first transparent region allowing etching to reach active layer, second insulating region blocking etching solution, and third transparent region allowing etching. This segmentation protects the active layer from corrosion while maintaining ease of metal electrode formation.
Solution Approach 2:
The gate electrode insulation layer acts as an intermediary between the etching solution and the active layer. It selectively controls the interaction by being transparent in some regions and insulating in others, preventing harmful etching solution contact with the active layer while allowing necessary etching in controlled regions.
2Object-affected harmful factors
If gate electrode insulation layer is made fully insulating, then protection from etching solution is improved, but electrical connection to active layer is blocked
Solution Approach 1:
The gate electrode insulation layer has different properties in different regions: the first and third regions are transparent to etching solution allowing electrical connection, while the second region is insulating providing protection. This local differentiation resolves the contradiction between protection and connection.
Solution Approach 2:
The insulation layer is segmented into functional zones: transparent regions for electrical connection and insulating regions for protection. This segmentation allows simultaneous achievement of both protection from etching solution and maintained electrical connection to active layer.
Data Source
AI summary
An embodiment of the present application discloses an array substrate and a manufacturing method thereof. The array substrate includes an underlay, an active layer, a gate electrode insulation layer, and a metal layer. A first through hole, second through holes, third through holes, and a fourth through hole are defined in the gate electrode insulation layer. The second through holes and third through holes are arranged at intervals such that partial regions of the active layer are shielded by the gate electrode insulation layer to prevent them from corrosion of an etching solution to guarantee a normal electrical connection of the active layer and a source electrode and a drain electrode and improve a yield rate of the array substrate.