Negative-Voltage ESD Protection Circuit Without N-Type I/O Connection
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Solution Overview
Problem
Conventional ESD protection circuits for I/O pins with negative voltage suffer from parasitic diode formation, leading to junction forward leakage current, which increases manufacturing costs due to the need for deep N-well isolation techniques.
Innovation Solution
An ESD protection circuit comprising a P-type device and a diode, where the P-type device is directly connected between the I/O pin and ground voltage, and the anode of the diode is connected to the I/O pin without any N-type doping/diffusion connection, eliminating the need for deep N-well isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If deep N-well isolation technique is used to isolate P-type diffusion and N-type diffusion, then junction forward leakage current is prevented, but manufacturing cost increases
Solution Approach 1:
The patent extracts the N-type diffusion from direct connection to the I/O pin, eliminating the parasitic diode formation between N-type diffusion and I/O pin. The ESD protection circuit uses only P-type diffusion devices (P-type diode and P-type transistor) connected to the I/O pin, while N-type diffusion is isolated through the P-type substrate, thereby preventing leakage current without requiring deep N-well isolation
Solution Approach 2:
The P-type substrate acts as an intermediary between the P-type diffusion devices and the N-type diffusion. The P-type transistor's source is connected to ground through the P-type substrate rather than directly connecting N-type diffusion to the I/O pin, preventing parasitic diode formation while maintaining ESD protection functionality
2Reliability
If conventional ESD protection circuit with diodes connected to ground is used, then ESD strike protection is provided, but parasitic diode formation causes leakage current in negative voltage operation
Solution Approach 1:
The patent inverts the conventional ESD protection approach by using P-type diffusion devices instead of N-type diffusion devices for the ESD protection circuit connected to the I/O pin. The P-type diode and P-type transistor are used to provide ESD protection, reversing the traditional doping type configuration to eliminate parasitic diode formation in negative voltage operation
Solution Approach 2:
The patent applies different doping types in different regions: P-type diffusion is used specifically for the ESD protection circuit components (diode and transistor) connected to the I/O pin, while N-type diffusion is used for other circuit elements not directly connected to the I/O pin. This local differentiation of material properties prevents parasitic diode formation at the I/O pin interface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration prevents junction forward leakage current and reduces manufacturing costs by avoiding the deep N-well process, while effectively absorbing short-duration voltage pulses during ESD strikes.
Implementation Method 1
these diodes absorb the short-duration voltage pulses during the ESD strike, that is high peak currents from the ESD strike flow to the ground through the diodes and limit the ESD strike voltages
Implementation Method 2
an anode of the first diode is directly connected to the I/O pin... the ESD protection circuit does not comprise any device whose N-type doping/diffusion is directly connected to the I/O pin
Data Source
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AI summary
The present invention provides a chip including an I/O pin and an ESD protection circuit. The ESD protection circuit includes a P-type device and a first diode, wherein the P-type device is coupled between the I/O pin and a ground voltage, and an anode of the first diode is directly connected to the I/O pin. In addition, the ESD protection circuit does not comprise any device whose N-type doping/diffusion is directly connected to the I/O pin.