3D Memory Channel Doping Layout for Select Transistor Reliability
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Solution Overview
Problem
The operational reliability of three-dimensional (3D) semiconductor memory devices deteriorates as the number of memory cell stacks increases, due to challenges in maintaining effective electrical coupling and channel current efficiency.
Innovation Solution
The semiconductor memory device incorporates a stacked body with interlayer insulating layers, conductive patterns, and channel structures that include undoped and doped semiconductor patterns, along with a gate insulating layer, to enhance electrical coupling and channel current stability, utilizing a method that forms these structures through alternating layers and sacrificial layers to ensure reliable gate-induced drain leakage (GIDL) current during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cell stacks is increased to improve the degree of integration, then the storage capacity is improved, but the operational reliability deteriorates
Solution Approach 1:
The patent applies local quality by creating distinct doped and undoped regions within the channel structure. The undoped region is positioned between the select line and core insulating layer to maintain proper electrical characteristics, while doped regions are placed at other locations to enhance carrier concentration and current efficiency. This localized differentiation resolves the reliability issue while maintaining high integration.
Solution Approach 2:
The patent changes the doping parameter along the channel structure, transitioning from uniformly doped to selectively doped regions. By controlling the doping concentration distribution - with undoped regions having zero doping concentration and doped regions having elevated doping concentrations - the patent optimizes both electrical coupling and channel current efficiency, thereby maintaining reliability in high-density configurations.
2Quantity of substance
If the number of memory cell stacks is increased, then the degree of integration is improved, but the electrical coupling efficiency deteriorates
Solution Approach 1:
The patent implements local quality by positioning undoped semiconductor regions at specific locations within the channel structure, particularly between the select line and core insulating layer. This localized undoped region maintains proper electrical coupling characteristics, preventing degradation even as the number of stacks increases to improve integration density.
Solution Approach 2:
The channel structure is segmented into distinct doped and undoped regions, allowing each segment to perform its specific function. The undoped segment maintains electrical coupling integrity, while doped segments enhance current efficiency. This segmentation enables the structure to scale to higher integration levels without compromising electrical coupling.
3Quantity of substance
If the number of memory cell stacks is increased, then the storage capacity is improved, but the channel current efficiency deteriorates
Solution Approach 1:
The patent applies local quality by creating doped regions within the channel structure at strategic positions. These doped regions increase carrier concentration and improve channel current efficiency, counteracting the degradation that would normally occur with increased stack density. The undoped regions are positioned to maintain proper electrical characteristics.
Solution Approach 2:
The patent modifies the doping parameter distribution along the channel, creating a non-uniform doping profile. By increasing doping concentration in specific regions while maintaining undoped regions elsewhere, the patent optimizes channel current efficiency even as storage capacity increases through higher stack density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the operational reliability of the semiconductor memory device by stabilizing channel current and turn-off characteristics of select transistors, ensuring efficient data storage and retrieval.
Implementation Method 1
forming a gate insulating layer by oxidizing a part of the doped semiconductor layer through the gate region
Data Source
AI summary
Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a stacked body including interlayer insulating layers and a select line disposed between the interlayer insulating layers, a core insulating layer penetrating the stacked body, a semiconductor pattern extending along a sidewall of the core insulating layer and including an undoped area disposed between the select line and the core insulating layer, doped semiconductor patterns disposed between the semiconductor pattern and the interlayer insulating layers, and a gate insulating layer disposed between the semiconductor pattern and the select line.