3D Memory Cell Structure With Separated Vertical Channel Patterns
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Solution Overview
Problem
Current semiconductor memory devices face challenges in enhancing the integration density of memory cells, particularly in three-dimensional configurations where efficient stacking and separation of channel patterns are crucial for improved performance and efficiency.
Innovation Solution
The semiconductor memory device incorporates a unique structure with first and second channel patterns extending vertically, separated by a channel separation pattern, and surrounded by conductive patterns, along with memory patterns disposed between these elements, allowing for enhanced integration and control through specific gate electrode configurations and bit line connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in three-dimensions on a substrate to improve integration density, then the degree of integration improves, but the complexity of channel pattern separation and control increases
Solution Approach 1:
The patent divides the channel structure into multiple independent channel patterns (first channel pattern, second channel pattern, third channel pattern) separated by distinct separation patterns. This segmentation allows each channel to be independently controlled by separate bit lines, enabling complex 3D memory arrangements while maintaining manageable control structures through modular organization of channels and their associated control elements.
Solution Approach 2:
The patent transitions from planar 2D memory cell arrangement to three-dimensional vertical stacking of channel patterns and memory cells. Multiple channel patterns are arranged vertically with conductive patterns stacked in the vertical direction, achieving higher integration density by utilizing the third dimension while maintaining electrical control through carefully designed bit line connections that access different vertical levels.
2Quantity of substance
If multiple channel patterns are stacked vertically to increase integration density, then memory cell capacity increases, but the difficulty of controlling and selecting specific memory cell strings increases
Solution Approach 1:
The patent segments the control structure by assigning separate bit lines to different channel patterns (first bit line for first channel pattern, second bit line for second channel pattern, third bit line for third channel pattern). This segmentation enables independent selection and control of memory cell strings within each channel, simplifying the addressing and selection process in vertically stacked 3D memory structures.
Solution Approach 2:
The conductive patterns serve multiple functions: they act as gate electrodes for controlling current flow in channel patterns, serve as separation structures between different channels, and function as part of the memory cell structure itself. This multi-functionality reduces the number of separate control elements needed, thereby simplifying the overall control mechanism while maintaining high integration density.
Data Source
AI summary
The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.