3D Charge-Trap Memory Structure for Preventing Charge Migration
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Solution Overview
Problem
Three-dimensional (3D) semiconductor devices face challenges in achieving excellent charge retention due to charge migration issues, which existing technologies have not adequately addressed.
Innovation Solution
The implementation of a 3D semiconductor device structure that includes a word line stack and channel pillars with specific layers such as central and tunneling dielectric layers, ring-shaped charge trap layers, and blocking dielectric layers, where the interlayer dielectric layers are used to prevent charge migration by isolating the charge trap layers from each other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge trap layers are used in 3D semiconductor devices, then data storage capability is improved, but charge migration occurs leading to poor retention
Solution Approach 1:
The charge trap layer is divided into multiple discrete charge trap layers (first charge trap layer, second charge trap layer, third charge trap layer) separated by interlayer dielectric layers. This segmentation prevents charge migration between trap layers while maintaining data storage capability in each layer.
Solution Approach 2:
Interlayer dielectric layers are introduced as intermediary structures between adjacent charge trap layers. These dielectric layers act as barriers that prevent charge migration between trap layers while allowing the trap layers to function independently for data storage.
2Quantity of substance
If multiple charge trap layers are stacked, then data storage density is improved, but charge migration between layers increases
Solution Approach 1:
Multiple charge trap layers are segmented and separated by interlayer dielectric layers, creating isolated storage regions. This allows high data storage density through vertical stacking while preventing charge migration between layers through the separating dielectric structures.
Solution Approach 2:
Interlayer dielectric layers serve as intermediary barriers between stacked charge trap layers, enabling high storage density through vertical integration while preventing harmful charge migration between adjacent trap layers.
3Reliability
If charge trap layers are isolated, then charge migration is prevented, but device structure becomes more complex
Solution Approach 1:
The device structure is segmented into modular units consisting of charge trap layers and interlayer dielectric layers. This segmentation achieves charge isolation and retention while maintaining manageable structural complexity through repeated modular patterns.
Solution Approach 2:
Interlayer dielectric layers are introduced as standard intermediary structures between charge trap layers. While this increases structural complexity, it provides necessary charge isolation and can be fabricated using established processes, balancing retention requirements with manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data retention characteristics by preventing charge migration between the charge trap layers, thereby improving the overall charge trap ability and retention of the 3D semiconductor device.
Implementation Method 1
The interlayer dielectric layer is in contact with upper and lower surfaces of the outer charge trap layer and is in contact with upper and lower surfaces of the blocking dielectric layer
Data Source
AI summary
A 3D semiconductor device includes: a word line stack over a substrate; and a channel pillar vertically penetrating the word line stack. The word line stack includes a word line and an interlayer dielectric layer. The channel pillar includes: a central dielectric layer; a channel layer surrounding a side of the central dielectric layer; a tunneling dielectric layer having a cylinder shape surrounding a side of the channel layer; an inner charge trap layer surrounding a side of the tunneling dielectric layer; a ring-shaped outer charge trap layer surrounding a side of the inner charge trap layer; and a ring-shaped blocking dielectric layer surrounding a side of the outer charge trap layer. The word line and the blocking dielectric layer have substantially the same vertical thickness. The interlayer dielectric layer is in contact with upper and lower surfaces of the outer charge trap layer and the blocking dielectric layer.