Solid-State Devices TRIZ Cases

A dual insulation stack in SPAD pixels reduces charge trapping at the isolation region to stabilize drive start voltage and detection reliability.

Shared photomask patterning forms electrode and transparent conductive layers together, cutting process steps and photomask cost.

A staggered Micro LED layout and black matrix through holes simplify electrode deposition for full-color quantum dot display panels.

A centrally symmetric vertical transfer gate shortens charge diffusion paths to reduce image lag and improve transfer uniformity in larger pixels.

Openings in the display panel edge conductor reduce peeling and moisture-driven corrosion while preserving power-pad connection reliability.

Interlayer dielectric barriers isolate stacked charge-trap regions in a 3D memory pillar to limit charge migration and improve data retention.

Curved gate cut regions reshape cell boundaries to preserve tolerances, save area, and place wider and narrower devices side by side.

Dipole-forming oxide and metal-oxide blocking layers in 3D memory raise electron tunneling barriers, improving programming efficiency and data retention.

Multiple diffusion layers with phosphor and ink particles broaden LED light distribution, reduce hot spots, and keep the module thin and flexible.

A shared nickel-palladium-gold plating process treats memory card PCB terminals and mounting pads together, cutting steps, cost, and gold use.

Different resistor values between main and control gates speed IGBT turn-off, cutting tail current without raising leakage or control complexity.

Multiple capacitors are stacked in one trench and coupled in parallel to raise chip capacitance without increasing pitch.

A stepped laminated via structure lets etching solution drain from through holes, reducing bubbles and improving array substrate conductivity.

Concave-convex active pillar surfaces enlarge gate oxide area to strengthen DRAM gate control and suppress short-channel effects.

A TFT sensing array under the display captures reflected optical signals for health detection without external sensors, cutting screen thickness and assembly complexity.

Different contact resistances and dual current spreading layers balance LED chip current and heat for more uniform light emission.

A stacked active-passive die architecture adds dense wiring to FPGAs, boosting memory bandwidth while cutting latency, power, and cost.

A corrosion-resistant intermediate electrode layer blocks oxidation during high-temperature baking, improving FeRAM switching and data retention.

Mesh-shaped touch electrodes and insulating layers improve bendability while preventing cracking in flexible display panels.

Via-connected light-shielding patterns stay level around light holes, preserving channel shape and improving optical fingerprint recognition.

Alternating high- and lower-doped drain regions create resistance that suppresses ESD voltage spikes and protects gate dielectrics in ICs.

Rough substrate surfaces and segmented light shielding improve LED light extraction while blocking color mixing between neighboring display cells.

Selective outer-pupil light shielding improves phase-difference autofocus while limiting image quality loss through signal correction.

A backside high-absorption structure cuts reflectance and optical cross-talk in BSI image sensors, improving quantum efficiency.

A single transferring through hole links the pixel and drain electrodes, raising aperture ratio and yield while reducing display defects.

Discrete oxygen-deficient ferroelectric layers and gettering liners ease 3D memory integration while improving endurance, memory window, and power use.

Adjusted gate-drain overlap balances sub-pixel kickback voltage, suppressing mura defects while preserving aperture ratio.

Selective etching exposes passivation pinholes in photo detectors, enabling abnormal units to be screened before field failure.

A controlled non-light-emitting ring around a light-transmissive sensor hole keeps the black edge uniform without sacrificing screen-to-body ratio.

Segmented electrodes and detoured contacts connect LED elements in series-parallel to raise display emission efficiency while avoiding shorts.

Light-shield layers placed over inter-subpixel regions block OLED light leakage despite layer misalignment, preserving color accuracy.

A homogeneous dielectric polymer protects smart card fingerprint sensors from sweat, humidity, and abrasion without degrading capacitive detection.

Wavelength-routing nano-structures focus incident light onto target pixels, cutting color-filter absorption losses while preserving color purity.

Patterned pad layers expose a visible bump contact region, enabling direct low-temperature bonding with reliable connection and less panel damage.

Dual Nb2N and Ta2N sacrificial layers let GaN chips move off costly SiC onto high-thermal-conductivity substrates with simpler transfer.

Segmented bridge routing in a TFT bending region avoids filling-layer holes, reducing metal line breakage and short-circuit risk.

A continuous two-level light-shielding structure blocks light leakage around display openings while avoiding extra cover-substrate parts.

A lower-coverage trench wiring layer cuts resistance while preventing bonding voids between stacked image sensor substrates.

Randomized opaque mounting areas and interconnect paths cut rainbow effects and diffraction spikes in transparent displays.

A conductive grid around photodiodes reflects light and isolates adjacent pixels, improving quantum efficiency and reducing cross-talk.

Different insulating-layer opening widths and spacing balance light extraction with current diffusion in high-power LED structures.

A transparent base carrier and absorption layer enable laser ablation de-bonding that speeds wafer separation without damaging the carrier.

Stacked and folded capacitors with shared nodes reduce charge disturbance and parasitic capacitance to improve ferroelectric memory retention.

A stacked light-emitting layout with wavelength conversion improves white color uniformity and optical efficiency across blue, green, and red light.

A three-layer OLED anode raises work function to improve hole injection while suppressing cathode short-circuit dark spots.

Varying electrode widths and floating electrodes reduce edge electric fields, keeping LEDs evenly distributed for uniform display emission.

Sequential dielectric films with different conductances preserve capacitance while blocking leakage current in compact semiconductor capacitors.

Multi-side global drive circuits cut IR drop and wiring delay, helping stacked CMOS image sensors keep exposure timing uniform.

Transparent ohmic contact, a conductive side arm, and a reflective dielectric layer improve micro LED light extraction and reflectivity.

Word line plates at each level and dual-electrode pillars avoid deep recesses, cutting memory array manufacturing time, cost, and reliability risks.