Solid-State Devices TRIZ Cases

A dual insulation stack in SPAD pixels reduces charge trapping at the isolation region to stabilize drive start voltage and detection reliability.

Shared photomask patterning forms electrode and transparent conductive layers together, cutting process steps and photomask cost.

A staggered Micro LED layout and black matrix through holes simplify electrode deposition for full-color quantum dot display panels.

A centrally symmetric vertical transfer gate shortens charge diffusion paths to reduce image lag and improve transfer uniformity in larger pixels.

Openings in the display panel edge conductor reduce peeling and moisture-driven corrosion while preserving power-pad connection reliability.

Interlayer dielectric barriers isolate stacked charge-trap regions in a 3D memory pillar to limit charge migration and improve data retention.

Curved gate cut regions reshape cell boundaries to preserve tolerances, save area, and place wider and narrower devices side by side.

Dipole-forming oxide and metal-oxide blocking layers in 3D memory raise electron tunneling barriers, improving programming efficiency and data retention.

Multiple diffusion layers with phosphor and ink particles broaden LED light distribution, reduce hot spots, and keep the module thin and flexible.

A shared nickel-palladium-gold plating process treats memory card PCB terminals and mounting pads together, cutting steps, cost, and gold use.

Different resistor values between main and control gates speed IGBT turn-off, cutting tail current without raising leakage or control complexity.

Multiple capacitors are stacked in one trench and coupled in parallel to raise chip capacitance without increasing pitch.

A stepped laminated via structure lets etching solution drain from through holes, reducing bubbles and improving array substrate conductivity.

Concave-convex active pillar surfaces enlarge gate oxide area to strengthen DRAM gate control and suppress short-channel effects.

A TFT sensing array under the display captures reflected optical signals for health detection without external sensors, cutting screen thickness and assembly complexity.

Different contact resistances and dual current spreading layers balance LED chip current and heat for more uniform light emission.

A stacked active-passive die architecture adds dense wiring to FPGAs, boosting memory bandwidth while cutting latency, power, and cost.

A corrosion-resistant intermediate electrode layer blocks oxidation during high-temperature baking, improving FeRAM switching and data retention.

Mesh-shaped touch electrodes and insulating layers improve bendability while preventing cracking in flexible display panels.

Via-connected light-shielding patterns stay level around light holes, preserving channel shape and improving optical fingerprint recognition.

Alternating high- and lower-doped drain regions create resistance that suppresses ESD voltage spikes and protects gate dielectrics in ICs.

Rough substrate surfaces and segmented light shielding improve LED light extraction while blocking color mixing between neighboring display cells.

Selective outer-pupil light shielding improves phase-difference autofocus while limiting image quality loss through signal correction.

A backside high-absorption structure cuts reflectance and optical cross-talk in BSI image sensors, improving quantum efficiency.

A single transferring through hole links the pixel and drain electrodes, raising aperture ratio and yield while reducing display defects.

Discrete oxygen-deficient ferroelectric layers and gettering liners ease 3D memory integration while improving endurance, memory window, and power use.

Adjusted gate-drain overlap balances sub-pixel kickback voltage, suppressing mura defects while preserving aperture ratio.

Selective etching exposes passivation pinholes in photo detectors, enabling abnormal units to be screened before field failure.

A controlled non-light-emitting ring around a light-transmissive sensor hole keeps the black edge uniform without sacrificing screen-to-body ratio.

Segmented electrodes and detoured contacts connect LED elements in series-parallel to raise display emission efficiency while avoiding shorts.

Light-shield layers placed over inter-subpixel regions block OLED light leakage despite layer misalignment, preserving color accuracy.

A homogeneous dielectric polymer protects smart card fingerprint sensors from sweat, humidity, and abrasion without degrading capacitive detection.

Wavelength-routing nano-structures focus incident light onto target pixels, cutting color-filter absorption losses while preserving color purity.

Patterned pad layers expose a visible bump contact region, enabling direct low-temperature bonding with reliable connection and less panel damage.

Dual Nb2N and Ta2N sacrificial layers let GaN chips move off costly SiC onto high-thermal-conductivity substrates with simpler transfer.

Segmented bridge routing in a TFT bending region avoids filling-layer holes, reducing metal line breakage and short-circuit risk.

A continuous two-level light-shielding structure blocks light leakage around display openings while avoiding extra cover-substrate parts.

A lower-coverage trench wiring layer cuts resistance while preventing bonding voids between stacked image sensor substrates.

Randomized opaque mounting areas and interconnect paths cut rainbow effects and diffraction spikes in transparent displays.

A conductive grid around photodiodes reflects light and isolates adjacent pixels, improving quantum efficiency and reducing cross-talk.

Different insulating-layer opening widths and spacing balance light extraction with current diffusion in high-power LED structures.

A transparent base carrier and absorption layer enable laser ablation de-bonding that speeds wafer separation without damaging the carrier.

Stacked and folded capacitors with shared nodes reduce charge disturbance and parasitic capacitance to improve ferroelectric memory retention.

A stacked light-emitting layout with wavelength conversion improves white color uniformity and optical efficiency across blue, green, and red light.

A three-layer OLED anode raises work function to improve hole injection while suppressing cathode short-circuit dark spots.

Varying electrode widths and floating electrodes reduce edge electric fields, keeping LEDs evenly distributed for uniform display emission.

Sequential dielectric films with different conductances preserve capacitance while blocking leakage current in compact semiconductor capacitors.

Multi-side global drive circuits cut IR drop and wiring delay, helping stacked CMOS image sensors keep exposure timing uniform.

Transparent ohmic contact, a conductive side arm, and a reflective dielectric layer improve micro LED light extraction and reflectivity.

Word line plates at each level and dual-electrode pillars avoid deep recesses, cutting memory array manufacturing time, cost, and reliability risks.

A compact RRAM device uses a conductive sidewall spacer to position variable resistance material layers between the gate electrode and the spacer.

Patterned substrate structure reduces warpage and minimizes damage to micro LED elements during mass transfer.

Mapping two adjacent physical cells as a single logical unit enables byte-level programming, eliminating sector erasure overhead.

Air gaps in wire grid polarizers reduce average refractive index to boost transmittance and extinction ratio.

Forming a lateral tunnel in the etch-guiding layer of an optical waveguide to create electric isolation.

Composite packaging materials with high resistivity resolve the trade-off between miniaturization and signal distortion in autonomous vehicle sensors.

A condensing unit with a deviated optical axis focuses reflected light onto a sensing unit to improve imaging quality.

Segmented vertical electrodes and varied-length connection lines increase integration density while reducing manufacturing complexity.

A semiconductor device uses a multilayer stack with a seed layer to stabilize the crystal structure of a high-k dielectric layer.

Lateral recesses isolate sacrificial layers from memory portions during etching, preventing collateral damage to the resistive material.

Support insulating layer fills concave portions of common source line to stabilize gate stacked structures in three-dimensional semiconductor devices.

A semiconductor memory device uses a deposition-inhibiting layer to selectively form conductive films on exposed insulating surfaces.

Introducing a low work function metal halide compound at the electrode interface reduces the hole injection energy barrier, enhancing device efficiency.

Embedding quantum dots in a mesoporous silica framework improves display uniformity while reducing energy consumption through low-voltage IGZO switching.

A light absorbing layer positioned on a display substrate absorbs stray electromagnetic radiation reflected by internal metal conductors.

Removing the substrate eliminates thermal barriers and reduces thickness, maximizing heat removal and electrical performance.

A composite nickel and gold layer structure reduces material costs while maintaining high corrosion resistance for reliable electrical connectivity.

Through hole wirings route connections vertically to resolve substrate area constraints.

A pressure detecting apparatus uses segmented driving circuits to sequentially activate sensing blocks, reducing standby power consumption.

Isolation pattern with vertical extension portions and connection segments reduces coupling between channel and dummy channel in vertical memory devices.

A CMOS pixel design with a floating sense node and transfer gate accelerates charge movement.

A semiconductor light-emitting device uses a resin outflow preventing portion to seal the element.

A semiconductor spacer patterning method defines fine patterns separate from mask patterns to improve device yield.

Hexaazatriphenylene hexacarbonitrile forms a stable organic cover layer that prevents cracks from foreign material damage.

A light extraction layer within pixel grooves refracts photons from OLED components through a thin film packaging structure.

Monoclinic zirconium quinolate reduces turn-on voltage and increases luminance compared to aluminium quinolate.

Silicon on insulator wafer process forms back-illuminated photodiodes with electrodes on the opposite side of the buried oxide layer.

A display panel uses overlapping emissive and reflective areas to emit light in opposite directions without a polarizer.

A temporary bonding laminate uses a liquid release layer to support semiconductor wafers during processing.

Gradient thickness soft material layers sandwich a rigid core in the backplate, preventing physical border line recognition while maintaining impact resistance.

Angled bottom electrode corners guide filament formation to reduce resistance distribution and read current variability in RRAM.

Patterned protrusions on a molded part refract light to enhance central illuminance in light-emitting element packages.

Floating substrates in a two-die isolation architecture enable large offset voltages while clamping ESD energy through breakdown diodes.

Segmented bridge wiring distributes accumulated electric charges away from the display area, preventing insulation breakdown and defective pixels.

Adjusting ink rheology with ionic conjugated polyelectrolytes prevents mutual solubility between adjacent layers during OLED manufacturing.

Sequential substrate bonding and removal form chips, enabling high pixel density optoelectronic devices without stringent transfer alignment.

Relocating the repair line connecting line to the outer side of the sealed plastic frame avoids excessive loading and insufficient charging rate.

Equal thermal impedances isolate the active region, reducing power consumption and interface failure risks.

A silicon nitride or oxide layer on organic banks resists fluorine compound affinity, preventing ink repellency and ensuring uniform light emission.

An oxide semiconductor layer stabilizes the pad interface in display devices.

Positioning contact pads inside the active region eliminates inactive zones, reducing CMOS image sensor size and cost.

A composite membrane uses graded-refractive-index layers to reduce light reflectivity and enhance transmittance in display devices.

A U-shaped channel element supports a gate electrode layer and surrounding memory elements to form vertical NAND strings.

Coordinated scanner and stage motion synchronizes laser pulses to create uniform spot intervals, resolving slow processing speeds in display manufacturing.

Capacitance canceling circuitry generates cancellation capacitance to neutralize signal dependent capacitance, reducing voltage-dependent parasitic distortion.

A light-emitting semiconductor chip relocates electrical contacts to the side surface, preserving top and bottom emission areas.

Shield layer overlaps bypass portions of conductive lines to prevent coupling and reduce non-display area while maintaining luminance uniformity.

A metal buffer layer matches link line reflectivity to hide non-display patterns, preventing visible line artifacts in borderless panels.

Integrates optical source and sensor modules on a cover body to reduce lengthy LED and sensor alignment during mouse production.

Segmenting the electron transport region with a dedicated control layer resolves injection imbalance, boosting OLED efficiency and lifespan.

A reflective grating redirects incident light toward a switch element within a detection panel drive circuit.

Multiple metal wires connect adjacent light emitting cells in an AC LED matrix to enhance light intensity and reduce flickering.

Oxidized blocking insulation layers separate independent charge storage segments to resolve reliability deterioration caused by charge movement.

Patterned thermal layers in OLED encapsulation transfer heat through sub-pixel openings, reducing thermal decomposition while blocking moisture and oxygen.

A white organic electroluminescent device uses blue organic fluorescent material as an energy-sensitized host to balance carrier distribution.

Segmenting coordination sites via a tetradentate ligand yields a bluer, narrower emission spectrum than conventional tris(bidentate) complexes.

Low viscosity and acidity prevent oxidation of gate lines and capillary flow into air gaps during wet cleaning.

A switching element uses asymmetric MOSFETs and parasitic diodes to form bidirectional current paths.

Alternating ramps and bumpy patterns segment the insulating layer to prevent residual film formation and backlight bleed in high-resolution displays.

Segmented Pechmann dye polymers boost field-effect mobility while maintaining solubility and air stability via controlled side chains.

Segmented side reflector surfaces redirect light to improve luminance uniformity while reducing optical depth and eliminating the bluish phenomenon.

A nonvolatile memory read method selects sensing manners based on vertical string channel length to ensure consistent electrical properties.

A semiconductor light detection device uses through-hole electrodes to connect quenching resistors across the substrate thickness.

Strategic mandrel openings minimize sidewall spacer deformation, preventing bit line defects while maintaining wide conductive line connectivity.

A porous encapsulation layer diffuses impurities across its structure, preventing localized concentration that causes dark spots and extends device lifespan.

Homogeneous polysilicon layers remove the top layer during etching, reducing process complexity and notch formation in semiconductor devices.

Segmented barrier walls block stray light between emitters and detectors, reducing signal crosstalk without increasing manufacturing costs.

Plastic deformation of support base bumps aligns light emitting elements during molding, reducing orientation variance and improving emission uniformity.

Metal-metal bonding transfers SiGe layers below 400°C, preserving component integrity while achieving high crystal quality.

A sensor panel uses mismatched shift pitches between neighboring sensors to minimize Moiré patterns in under-display fingerprint systems.

Stacked capacitor electrodes in a pixel structure increase storage capacitance while avoiding data line overlap that worsens power consumption.

Monolithic gate driver integrates capacitance portion using transparent conductive layers to reduce circuit area in active matrix substrates.

Fabricating high-resolution features in deep silicon cavities using contact lithography focusing patterns for precise microfabrication.

An OLED pad electrode structure uses an insulation pattern to protect the contact surface.

Electrolysis dissolves a thin-film metal layer to separate a flexible substrate from a rigid base, preventing mechanical damage during peeling.

Varying gate electrode line width across regions equalizes cross-sectional areas, reducing line resistance irregularities and preventing luminance loss.

Exposed silicon carbide surfaces with high water contact angles reduce stiction in MEMS devices, enhancing fabrication yields and device reliability.

Increasing separation between selected and isolation word lines suppresses high lateral electric fields, minimizing program disturb near the drain select gate.

A semiconductor device design standardizes insulation layers across cell and peripheral regions to simplify manufacturing.

Merging separate materials into a single ribbon resolves fabrication complexity while enhancing optical emission efficiency.

A vertical organic transistor uses a central electrode with integrated doping layers to enhance charge carrier transport efficiency.

Holed organic insulating layers extract gases from display areas to maintain light emission reliability.

Through-silicon vias and metal heat sinks conduct thermal energy away from the silicon substrate, minimizing dark current and improving signal-to-noise ratio.

Isolated partitions with lower refractive index surround color filters to enhance quantum efficiency peaks in image sensors.

Diagonal transistor placement allows selective gate line cutting at dedicated connection points, preventing data line cutoff during short circuit maintenance.

Composite glass frit paste resolves ohmic contact limitations to boost solar cell conversion efficiency.

A semiconductor memory device applies refresh pulses to chalcogen layers to maintain stable resistance states.

Ink jet printing forms semiconductor and gate insulating layers using a single bank, eliminating photolithography masks to reduce manufacturing complexity.

A variable resistance memory device uses distinct threshold voltages for near and far memory cells to balance electrical characteristics across the core region.

Sheltering means on packaging gel shoulders block optical noise, extending sensing distance while maintaining molded cap simplicity.

A dummy cell array with segmented gate lines and filling patterns enhances pattern uniformity in semiconductor devices.

Integrating a memory structure with a transistor via a bottom plate contacting the channel layer simplifies BEOL processing and enhances cell density.

Composite silicon and fluorine polymer print layers block uncured resin infiltration, maintaining color stability during UV curing processes.

A negative-type photosensitive resin composition combines polyimide and polysiloxane resins to form cured films with high-resolution patterns.

A conductor support member fills the gap between touch and display substrates to provide a stable mounting surface for electrical connections.

Peripheral deep trench isolation blocks optical and electrical crosstalk between adjacent pixels, increasing fill factor without reducing sensitivity.

Integrating touch sensors within the OLED stack bypasses Thin Film Encapsulation limits, expanding flexible display applicability.

Circuit board electrode pads arranged in rotational symmetry around a mounting pivot point.

A split-gate memory cell structure forms dedicated contact regions using self-alignment techniques to simplify manufacturing steps.

Replacing precision support pins with a transparent resin layer eliminates manufacturing complexity while maintaining structural stability.