NAND Flash Word Line Isolation for Program Disturb
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Solution Overview
Problem
Conventional programming schemes, such as Erased Area Self Boosting (EASB), face increased high electric field-enhanced program disturb when programming cells closer to the drain side select gate, leading to excessive vertical and lateral electric fields that worsen as memory cells are scaled down.
Innovation Solution
Separating the isolation word line from the selected word line by a larger distance, typically increasing the number of word lines between them as programming progresses towards the drain side select gate, to reduce excessive boosting and minimize high electric fields, which can be combined with existing boosting methods like EASB.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional programming schemes like EASB are used, then programming speed and efficiency are improved, but high electric field-enhanced program disturb increases when programming cells closer to the drain side select gate
Solution Approach 1:
The patent segments the word lines into different groups based on their distance from the drain side select gate. Different isolation schemes are applied to different segments: for word lines closer to the source side, the conventional EASB scheme is used, while for word lines closer to the drain side, an enhanced isolation scheme with additional word lines separated by larger distances is applied. This segmented approach allows the system to maintain high programming speed while reducing program disturb in critical regions.
Solution Approach 2:
The patent applies different isolation qualities to different spatial locations within the memory array. Specifically, larger separations and additional isolation word lines are applied locally to regions closer to the drain side select gate where program disturb is more severe, while conventional isolation is sufficient for regions closer to the source side. This local quality adjustment optimizes the balance between programming efficiency and reliability in different areas.
2Quantity of substance
If memory cells are scaled down to increase storage density, then storage capacity is improved, but vertical and lateral electric fields increase causing excessive program disturb
Solution Approach 1:
The patent applies preliminary isolation actions by selecting specific word lines to serve as isolation word lines before the actual programming operation. These isolation word lines are positioned at strategic distances from the selected word line to preemptively reduce the buildup of high electric fields. By establishing this isolation structure in advance, the system prevents excessive program disturb before it occurs, enabling safe scaling to higher densities.
Solution Approach 2:
The patent introduces intermediate word lines that act as mediators between the selected word line and the drain side select gate. These intermediate isolation word lines buffer and distribute the electric field, preventing concentration of high fields in scaled-down structures. The intermediary structures allow the system to maintain lower effective electric fields even as cell dimensions are reduced for higher storage density.
3Power
If the isolation word line is placed close to the selected word line, then boosting efficiency is improved, but high lateral electric fields increase causing program disturb
Solution Approach 1:
The patent implements a dynamic isolation scheme where the distance and positioning of isolation word lines are adjusted based on the position of the selected word line relative to the drain side select gate. For selected word lines closer to the source side, isolation word lines are placed at conventional distances to maximize boosting efficiency. For selected word lines closer to the drain side, the isolation word lines are positioned at larger distances or additional isolation word lines are introduced to reduce lateral electric fields. This dynamic adjustment optimizes the trade-off between boosting efficiency and program disturb reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses high electric fields and minimizes program disturb by maintaining adequate channel capacitance and reducing the vertical and lateral electric fields, thereby improving the reliability of programming operations, especially in scaled NAND devices.
Implementation Method 1
The control gate lines (CG) are typically formed over the floating gates as a self-aligned stack, and are capacitively coupled with each other through an intermediate dielectric layer 19
Implementation Method 2
high electric field-enhanced program disturb when programming cells closer to the drain side select gate, leading to excessive vertical and lateral electric fields
Data Source
AI summary
In an improved EASB programming scheme for a flash device (e.g. a NAND flash device), the number of word lines separating a selected word line (to which a program voltage is applied) and an isolation word line (to which an isolation voltage is applied) is adjusted as a function (e.g. inverse function) of distance of the selected word line from the drain side select gate to reduce program disturb due to high vertical and lateral electric fields at or near the isolation transistor when programming word lines closer to the drain side select gate. The selected and isolation word lines are preferably separated by two or more word lines to which intermediate voltage(s) are applied.